Month: May 2020

Layout automation: achievable or illusory?

by Sowmyan RajagopalanBlogNews

We are extremely successful efficiently migrating, refining and optimizing existing IP for new technologies and applications. Specifically, we are able to reduce the number of iterations it takes to get from our starting point – analysis of the process technology – all the way to layout migration.

However, layout migration is one step that remains very challenging and it’s worth taking a little time explaining why it remains resistant to automation.

Firstly, layout migration is never uniform: it’s almost by definition a custom design process, in fact. If you move from, say, one semiconductor platform to another or from 40 nanometre to 28 nanometre, it’s not just the names and numbers that change – the chip’s characteristics also change.

The layout needs to factor in those aspects: the way the devices are placed, the metals, the routing, how the chip is configured. But that’s not all. The way you position or place the structures on the layout is also going to have an impact on circuit characteristics. So too is the size of nodes.

Essentially then, the size of the chip is dependent on how you put together the layout – and the factors you are dealing with are not uniform.

Design simulation is also affected. Schematic-level simulations and layout simulations were once comparable. Now they are diverging – mainly because there are various elements that schematic-level models cannot factor in.

Capacitance is another issue. There are fancy equations to explain this but, put very simply, it’s about ever smaller conductor-to-conductor spacing and the knock-on effect of parasitic capacitance, which impacts the frequency ranges and the circuit characteristics. Parasitics in these ever-smaller dimensions have become a big issue.

All of which explains why full-on layout automation is so challenging: it needs to address all the problems layout design can throw up. The reality is it can’t.

But that’s no reason to abandon automation entirely. Our IP re-use platform tool – AMALIA – does not generate a complete layout factoring in all circuit characteristics, device sizes and parasitics. For the moment, that is impossible.

However, generating a base framework that compares with the base design in aspect ratio, device placement and routing of main signal nodes will assist the layout designer with a good starting point. About 20-25 per cent of the layout work should be speeded up when we reach this point. This should happen in the next 12 months.

The goal is to have something that builds a basic framework of the layout. And if you can offer that you will reduce the amount of time a layout designer would have to spend then putting together the layout.

Thus our aim is targeted automation – and that is achievable. What isn’t achievable – and may never be – is an all-singing, all-dancing layout automation tool. If someone offers you that, be very, very wary.

Wi-Fi 6: new challenges – and an adaptable process

by Sowmyan RajagopalanBlogNews

The new wave of wireless is here. Known as Wi-Fi 6 (or, less thrillingly, 802.11ax), it delivers four times faster average throughput compared to Wi-Fi 5 with greater than 5 Gb/s data rate capability. That’s a maximum of 9.6 Gbps – theoretical, of course, though the headline rates are still impressive.

Wi-Fi 6 also supports a much larger volume of mobile devices in dense deployment environments (large public spaces like arenas and airports), and it does so more efficiently. If multiple end users (including IoT end users – that is, things as well as people) are being served in a busy environment, Wi-Fi will be able to cope a lot better than its predecessors – and with less drain on batteries or diminishing of battery life.

Wi-Fi 6, as one commentator puts it, couples the freedom and high speed of gigabit ethernet wireless with the reliability and predictability of licensed radio, not least thanks to its use of the channel access mechanism known as orthogonal frequency division multiple access (OFDMA).

It’s the latest innovation from the Wi-Fi Alliance, the industry organisation that since its formation in 1999, has grown with the technology to become a major driver of new Wi-Fi applications and products.

Wi-Fi is one of the most widely implemented and deployed technologies ever invented – and the new iteration shows every sign of continuing that trend. But despite the ubiquity of Wi-Fi, designing RF, analog and mixed signal blocks for Wi-Fi remains a challenge for the engineer – and it isn’t going to go away with the arrival of Wi-Fi 6.

For example, at some point will be required to take this specific version of Wi-Fi 6 and move it from one manufacturing process to another, if a customer so desires, to help that customer lower cost, reduce power consumption, improve performance or enhance manufacturing flexibility, for example.

Let’s be clear about this: we’re not moving from Wi-Fi 4 or Wi-Fi 5 to Wi-Fi 6. That would be an architecture change. This is about shifting manufacturing processes coupled with design improvement – within the technology.

Will dealing with Wi-Fi 6 mean that our work process becomes slightly more expensive or takes more time than before? Perhaps. But it will still be cost-effective, and thus the whole point of analog IP reuse will still be valid.

But, like Wi-Fi, we are constantly improving. We have been able to reduce the number of iterations it takes to get from our starting point all the way to eventual layout migration – and we are continuing that improvement process. We also have a lot of relevant experience to draw on and build on, most notably in dual band Wi-Fi and Bluetooth. This will help us to help our customers to find the cost-effective approach they need, which is our aim in every job we take on – even when it involves a brand-new evolution of Wi-Fi.

We are aware that Wi-Fi 6 will offer new challenges. But the process we will be applying is one in which we are well versed and which can be adapted to this new wave of wireless – if you have the skill and the experience. And we have both.