Preserve layout integrity with intelligent automation
Streamline design layout, ensure compliance
AMALIA Layout Automation (LA) integrates critical verification data into the final layout, ensuring that design integrity is preserved after silicon validation.
Building on the optimized designs from Design Enabler, LA automates routine layout tasks, maintaining accurate placement and floorplan, LA streamlines the design process and ensures compliance with design constraints, ready for manufacture.
Verification-driven design continuity
Utilizes verified design data to maintain consistency in the final layout, enhancing the effectiveness of the design process.
Consistent floorplan management
Adheres to established placement and floorplan throughout the design evolution, upholding the design’s foundational structure.
Efficient task automation
Reduces the design timeline by automating labor-intensive tasks, allowing for a focus on strategic design aspects.
Reliable design rule checks
Automates DRC checks to ensure layouts meet critical standards, reducing the need for manual revision.
- Intuitive design interface: Tailored to the designer’s needs, the UI facilitates straightforward interaction and complements existing EDA workflows.
- Precise device and layer mapping: Streamlines the transition from design to physical layout by accurately mapping devices, properties, and layers.
- Automated compliance assurance: Executes automated DRC checks, ensuring layout adherence to industry standards and specifications.
- Harmonized design integration: Fits seamlessly within the standard EDA tool environment, providing a cohesive and uninterrupted design experience.
Quickly identify similiarities and difference between technologies
Automatically migrate complex circuits faster with less risk
Accelerate layout design and maintain quality with automated mapping and DRC checks
Optimize design centering more efficiently after migration
AMALIA in action
Rapid Tier1 to Tier2 migration analysis for 13 PMIPs facilitates second sourcing approach
Thalia’s partnership with a leading IP company to evaluate the potential migration of 13 Power Management IPs (PMIPs) from Tier1 to Tier2 40nm CMOS technology has set new benchmarks in pre-migration planning efficiency with a 75% reduction in time against a standard manual analysis.
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Whether you require a comprehensive, end-to-end solution or prefer a more autonomous approach, we are committed to identifying the most suitable partnership model to meet your specific needs.