How repeat IP reuse delivers significant savings

When IP reuse is implemented quickly and easily, small cost savings can turn into good profit margins. Thalia Chair Rodger Sykes explains how when you maximize the number of repeat reuses, you also maximize the potential for efficiencies and cost savings.

The development of a new chip involves significant upfront costs and investment. The higher the complexity, the greater those costs and the more difficult it can be to make profit. Product marketing teams look to product diversification, differentiation or simply expanding or updating their range of products to maximize the potential for profitable reuse – all which potentially can, or must, be replicated across multiple process technologies.

If we’re talking about the economics of our business model, let’s state clearly upfront: whichever way you look at the economics, analog IP reuse is a cost-effective strategy in process migration. Using Thalia’s AMALIA IP Reuse platform, our customers are able to reduce the time and the costs of their IP reuse and this can save up to 40% which enables them to not only cover all of the initial design and the reuse, but to make a good profit.

While developers do appreciate how IP reuse can increase profitability and help them to recover some of the costs – they are often still often left wondering why they have only covered development costs and can barely break-even.

Quantifying the level of cost saving is not always straightforward: for a start the savings are not only $ savings. Competitive advantages in terms of time-to-market, and design time saved, or simply the reduction in component or IP costs are all significant factors.

Still sounds straightforward, doesn’t it? Saving money or time, amounts to the same thing, right? And it’s all positive. Well, yes – and no.

Savings are all positive, but there are other approaches to design that can also save money and/or time. Developing a clearer understanding of the potential benefits of IP reuse means maximizing the potential savings.

It’s when IP reuse is implemented quickly and easily that small cost savings turn into profit margins. When you also maximize the number of repeat reuses you maximize the potential for efficiencies and cost savings.

Looking at the mix of our customers we can examine where the greatest gains are consistently made. Firstly, it’s the speed of implementing IP Reuse using Thalia’s AMALIA platform that makes a significant difference to those timescales. Secondly, the economic arguments supporting IP reuse are fundamentally economies of scale – and the numbers get really interesting when a continued reuse strategy is at the heart of customers’ design strategy.

Just isolating cost savings, we can see that casual, ad hoc reuse might deliver savings of the order of 2-3X. But, when design teams plan intelligent repeat reuse of IP blocks, across multiple designs, ported to multiple processes – and then go a stage further and apply this across the entire product portfolio – savings ramp up quickly. Design costs decrease exponentially with each instance, or each generation of reuse. Beyond a sixth reuse, customers tell us costs become insignificant – the savings and benefits are significant.

Beyond the financials, the design team’s familiarity with specific, trusted IP can count for significant economies in terms of efficiencies: saving design time, eliminating headaches and enabling the team to reach the optimum final design, ported to new processes in the shortest possible timescales.

If design reuse applies automated intelligent tools, employing self-learning AI tools, such as the Thalia’s AMALIA Design Enabler, then this further enhances time and cost savings as the tools will benefit from existing acquired intelligence, finding its way to the optimum design solution in the least possible time.

Solving the problem of growing ASIC respins recently reported on an industry survey showing an increase in respins due to analog circuitry failing or falling out of operable range.

The reasons behind this trend are complex, but the article suggests it comes down to analog tuning – the process of tweaking a design to maximise performance while staying within the operational parameters of the overall circuit. The article also explains that the chief scientist at Mentor, a Siemens Business, analysed the results to determine the scale and scope of this trend – whether it was affecting newer designs on the latest technology nodes, or if it was a universal problem.

Figure 1: Flaws contributing to ASIC re-spins. Source: Wilson Research and Mentor, a Siemens Business

It would be easy to assume that the problem was relating to newer nodes and newer processes, but on review, the issues are affecting technology nodes from sub-7nm to 150nm and higher.

Figure 2: Tuning analog circuit flaws by design size. Source: Wilson Research and Mentor, a Siemens Business

So what’s causing the increase in failures?

Put simply, the complexity of new devices. The number of complex devices is growing, and is set to continue with the expansion of the IoT. Automotive components are also massively on the rise, both in number and complexity, thanks to the developments towards self-driving cars. Companies are trying to fit all circuitry on the same substrate or on a single technology node and schematic simulation isn’t able to accurately assess function and full parameters.

Fig 3: Defect rates for automotive ICs and causes of failures. Source: Mentor, a Siemens Business

There will always be issues arising when working with new nodes and there is a learning curve for design teams to fully come to terms with the limitations, issues and particular traits displayed by these new nodes. Implementing this knowledge into toolsets is only achievable once they are fully understood. But if that learning curve therefore involves respins and ‘back to the drawing board’ moments at increasing frequency, then time to market will be affected for new devices. And increasing time to market for a new chip in a competitive industry can be the difference between market success and failure. Second place really is the first loser.

As IP reuse specialists, this is not news to us. We have worked with many clients evolving analog IP from one technology to another or even from one foundry to another. Most engagements are accompanied with the need to improve power consumption, speed, performance or the physical size of the silicon chip, and when these needs are implemented, they have knock on effects to other characteristics, resulting in the silicon not performing to specification.

We know this; it’s what we do. It’s why we developed our technology analyzer to be able to identify differences between base and target technologies and highlight where a circuit will fail. Our Trifecta, including the AMALIA platform, helps to identify the root cause of an issue and allows our design engineers to nudge a design back into specification before migration; mitigating the need for respins for out-of-tolerance circuits.

As experts in reusing analog IP on different process nodes or technologies, we’ve spent years developing processes to ensure IP works as expected and as needed in target technologies. We do this by deploying our Trifecta – advanced development methodologies, the targeted automation of our AMALIA platform and our design expertise. Using this Trifecta approach means we can verify IPs and their behaviour or performance before migration. Part of the AMALIA platform uses our proprietary technology analyzer to rapidly identify parameters in both base and target technologies to identify issues, allowing our expert designers to tweak characteristics and knock the design into specification.

This methodology, used by us across multiple technology nodes and foundries, has the potential to play a significant role in the fast and efficient migrating of analog IP for the ever-increasing number of IoT, mobile and handheld devices. Analog components sit alongside digital and ensuring everything functions as it should is key in getting new products to market ahead of the competition.

Technology Analyzer transforms analog IP reuse

A significant upgrade to Thalia’s AMALIA IP reuse platform cuts the cost of qualifying IP in a target technology. Thalia Design Automation, experts in targeted automation for analog and mixed signal design and IP reuse, today announced the launch of its Technology Analyzer, a further enhancement of its AMALIA IP reuse platform.

Much of the effort involved in migrating an IP from one technology to another is associated with qualifying the IP in the target technology. If a block fails to meet the requirements in the target technology, its response would be sub-optimal or would make the block unusable.

With traditional methods, identifying such issues can be extremely time consuming.  Thalia’s Technology Analyzer is the latest enhancement of its AMALIA IP reuse plus platform. It rapidly and accurately identifies the root cause of discrepancies between base and target technologies, allowing a solution to be implemented much more rapidly than in conventional analog IP design.

“This latest evolution of our AMALIA platform is a game changer,” said Sowmyan Rajagopalan, Thalia Design Automation CTO. “Whenever a key specification is not being met in the target technology, we have to determine the process technology or circuit characteristic responsible. By using our automated Technology Analyzer, we can take a design-centric approach to rapidly analyze and compare base and target technologies to see where the process technologies are similar and where they differ the most.”

The AMALIA Technology Analyzer addresses a comprehensive array of first and second order effects including FT, gm/id, Vdsat, Vt mismatches and others.

AMALIA’s Technology Analyzer helps clients assess whether or not IP is fit for purpose or suitable for cost-effective migration – a technology assessment solution essential in the selection of external IP and target process.

Read our new white paper to understand more about Thalia’s Technology Analyzer.

Design Considerations

Let’s say that a company buys into our IP reuse proposition. What is the best use of our technology in relation to its portfolio?

First and foremost the market defines everything. Every semiconductor company that designs more than one ASIC has to choose whether to build the portfolio or design new IPs. There are many factors that could potentially impact a decision but from a market point of view it’s all about the revenues these IPs or ASICs could generate – and that is about what the market wants and will pay for and a company’s relationship with its customers.

If an IP that a company builds in a new technology can generate a reasonable amount of money, then the number of licenses or units it sells before it recovers the cost could justify the work.

That in turn is driven by the number of resources required. Should third party help be sought.

What about opportunity cost? Does one choice completely negate another?

You might think that Thalia can impact every one of these considerations. You would be wrong. But there is still a lot we can do.

The cost to redevelop an analog or mixed signal complex IP block can be between half a million to a million Euros, that raises some obvious questions. Can enough licenses be sold to justify the outlay and make a profit? But if the cost to get that IP in silicon validated came down by up to 50%, that’s a game changer. That is something we might be able to help with. Our focus on targeted automation – which we are constantly evolving and improving – means we are able to reduce the design cycle time and hence the cost.

What about resources? How can a company identify them and bring them on board? If a third party–like Thalia – can do that, it might speed up the process and save money.

Opportunity cost, meanwhile, doesn’t need to be either/or. If you have your IPs in different nodes and technologies you don’t need to think in such absolute terms.

A company can look at all of these factors and choose a vendor, though first ensuring that the vendor can scale up to meet its requirements and do so reliably. And if that’s something you are considering, don’t forget to check the vendor’s bona fides and its reputation too. Has it ever promised more than it can deliver?

We have not. We understand our skillsets, the focus of our expertise and t the technologies we work with (though we are constantly evolving on all fronts). We also know that, if the time, place and customer needs fit our offering, then a shorter design cycle in a shorter time – and thus lower costs – are part of our USP.

Funding technology start-ups: stand out for success

Rodger Sykes, Thalia Chairman and CEOHaving just closed our largest funding round to date for Thalia I thought now would be a good time to reflect on the process and the environment.

Like most start-ups, at Thalia we have been through times when things didn’t go to plan. Getting heard and securing customer engagement is always a big challenge in any business.

But the tough times can make you stronger. By listening to customers and refining our offering and business model, we are now seeing strong interest in our analog IP migration and reuse capability. We’ve identified a real business need: and of course that’s one of the keys to convincing any investor to back your company.

In our case, we’ve understood that helping customers move functionality between processes and between foundries is a key capability for cost reduction and security of supply. We can help the trade off all business managers face between deploying valuable internal experienced resource on new IP development or cost reducing existing IP. We turn the latter into a clearly understood and bounded cost and let the internal designers focus on what they enjoy the most – and where they add most value – developing new circuits.

It is a common belief for early stage companies in the tech sector that it’s VERY hard to raise equity funding. In fact in my experience it’s not. Things continue to be very buoyant in the UK given the strong tax incentives available to investors through EIS and SEIS schemes.

There is a great deal of money around looking for a good investment. But “good” is the key word. Good is partly about the strength of the opportunity, but also about how the story is presented. If you have a less than good story and it’s presented badly, then funding is really hard. So if you’re having trouble, don’t blame the VCs.

Far too many founders focus on the technology, as that is their interest and comfort zone. It’s vital to look at the view from the investor’s side of the table. Most investors see hundreds of plans per month; they rarely understand the technology, it’s about return on their investment. VCs are generally not philanthropists. The key is to stand out. A strong exec summary is a key marketing document; that’s vital to get a face-to-face meeting.

Investors look for proof of a large market and customer interest, defensible IP (in case you really have something big), a team that has experience of building a company and so knows what they are doing (founders or advisors), and a financial plan that says you have thought through how much you need to get to break even and where you are going to spend it. Painful as it is for any early stage team, financials are THE common language across EVERY investment, so that’s an area where it’s good to have put in the effort.

It’s a lot to think about, and to do: securing our latest funding round means that Thalia has ticked all of those boxes. It also shows that you should never be afraid to explore new business models or change if you identify an attractive opportunity.

The key above all, however – once you get beyond the first 2-3 rounds of funding to get over the chasm – is customer revenue. Orders and revenue say customers are willing to pay for whatever you have. So as long as there is a global market to scale into, investors will line up.

And if, like Thalia, you have all those bases covered, the venture capital community will welcome you with open arms.