Disruptive AI-powered Layout Automation software launched as part of Thalia’s latest AMALIA platform release

Thalia, a leader in analog, mixed signal and RF IP design migration, today announced the release of AMALIA 24.3 with the first preview of its AI-powered layout porting software, the fourth component available in the comprehensive IP reuse platform.

Customers can now benefit not only from the ground-breaking Technology Analyzer and Circuit Porting suite, as well as the Design Enabler (core), but also the Layout Automation (LA) software which is the final stage in the process of providing designs to the foundry.

The AMALIA LA software uses the source design’s layout as the starting point and this unique approach facilitates the software to maintain the floorplan placement and preserves all intelligence generated on the existing IP through silicon validation. This is then tied with DR checks to ensure the final layout is DRC clean.

Sou Bennani-McCord, VP of Sales at Thalia, said:

“Today is another milestone for Thalia as we introduce our final solution to complete the AMALIA flow allowing customers to take their existing IPs from process technology analysis, porting of schematics/test benches to verification including estimated parasitics, to migrating the layout in the target technology.

“What we have today is a complete end-to-end IP reuse/migration platform that is the most comprehensive on the market and offers our customers best-in-class IP reuse that is fast, cost-effective and accurate. We look forward to introducing the new LA tool to our existing customers this month before launching it to the broader market early next year.”

The AMALIA 24.3 release includes other improvements to the platform such as enabling Key Device Identification to assist with meeting key design specifications in the AMALIA Design Enabler. It also includes DesignSync version control supporting customers’ design workflow in AMALIA Circuit Porting.

AMALIA is Thalia’s comprehensive end-to-end IP reuse software platform. Leveraging automation and AI/ML capabilities, it drastically reduces the complexity, cost and time traditionally associated with migrating and optimizing existing applications. Customers can make use of a discrete component of the AMALIA platform or leverage the complete platform providing them flexibility in how to manage their design migration requirements.

To find out more about the AMALIA Layout Porting, or to try the AMALIA platform, visit www.thalia-da.com

Thalia’s AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%

Thalia, a leader in analog, mixed signal and RF IP design migration, today announced the 24.2 release of its AMALIA platform. The latest update brings advanced features to the AMALIA toolset including estimated parasitics for enhanced design accuracy and a faster migration process for semiconductor IP design engineers.

AMALIA 24.2’s stand-out feature directly tackles one of the most intricate challenges in semiconductor design—accurate parasitic estimation. AMALIA eliminates this traditional constraint and streamlines the design process by intelligently incorporating extracted parasitics from the source design and including them in the circuit porting phase to provide estimated parasitics early in the design process. As a result, the accuracy of the ported schematic is improved, reducing the need for multiple post-layout parasitic extraction (PEX) iterations by at least 30%. This is particularly beneficial in high-frequency applications, and smaller process technology nodes, where precision and speed are paramount.

With this latest enhancement to the AMALIA platform, Thalia once again demonstrates its dedication to reducing design cycle times and associated costs, empowering businesses to achieve faster time-to-market for new product innovations. The new feature streamlines the schematic porting by removing the need for skilled designers to estimate parasitics manually, saving valuable resources and speeding up the design verification process.

Syed Ahmad, VP of Product Development at Thalia, remarked on the update, “With AMALIA 24.2, we’re not just updating a platform; we’re setting a new industry standard for efficiency and precision in IP migration. Estimated parasitics in AMALIA is a testament to our commitment to innovation and the tangible benefits it brings to our customers.”

In addition, AMALIA 24.2 enhances the IP migration experience with a new design centering assistant feature, and updates to its advanced device mapping. The design centering assistant quickly identifies critical devices that impact performance, facilitating precise adjustments, while the device mapping table now benefits from AI/ML-driven auto device recommendations, ensuring optimal device selection and removing the need for manual work.

The launch of AMALIA 24.2 is a pivotal moment for design engineers looking to navigate the complexities of semiconductor design migration with greater ease and accuracy. Thalia remains at the forefront of this endeavor, continuously seeking ways to refine and enhance the IP design migration process to deliver tangible value to businesses trying to maximize their team resources and productivity.

Find out how AMALIA 24.2 can facilitate your IP migration projects, saving both time and budget.

AMALIA 24.1 releases with support for 12nm FinFET alongside major enhancements to its Circuit Porting and Technology Analyzer tools

Thalia, a leader in analog, mixed signal and RF IP design migration, today announced the release of AMALIA 24.1. This latest version of the company’s efficient IP reuse and migration platform includes the recently announced support for 12nm FinFET technology and Circuit Porting simulation comparisons. Also introduced in this update is a summary report within AMALIA’s Technology Analyzer software. Using this report, key decision makers can quickly access the critical information they need to choose the right process technology nodes and optimum devices, streamlining the decision-making process.

“Integrating support for 12nm FinFET technology into AMALIA was an important step forward in ensuring our customers have the capabilities needed to use advanced process technologies,” explained Syed Ahmad, VP of Product Development at Thalia. “FinFET technology is crucial for developing semiconductor devices that are not only smaller, more efficient, and more powerful but also designed to meet the stringent requirements of advanced technology nodes. This enables their use in a wide range of applications, from consumer electronics and automotive systems to the Internet of Things.”

In addition to the support for 12nm FinFET technology, AMALIA 24.1 offers simulation comparison capability within its Circuit Porting tool. With this feature included, IP designers can not only port designs to new process nodes, they can also simulate and compare the outcomes of the original and ported designs, using their preferred simulator tool and see if any further adjustments are needed. This reduces the requirement for multiple iterations and saves design porting time.

A new feature included within the AMALIA 24.1 release is a report that provides a summary of the in-depth results from AMALIA’s Technology Analyzer findings.

“This latest enhancement to our software suite uses AI to provide a concise summary of key findings and recommendations taken from the standard report which, due to its comprehensive nature, can be hundreds of pages long. This drastically reduces the subsequent analysis time by providing the most relevant and critical information in a format that is quick and easy for senior designers and key decision makers to understand and make informed decisions,” Syed Ahmad explains.

The release of AMALIA 24.1 reflects Thalia’s dedication to supporting the semiconductor industry’s evolving needs, by not only maintaining up-to-date technology support but also by innovating and enhancing the user experience through new features that simplify complex processes.

For more information on how AMALIA 24.1 can facilitate your IP migration and optimization projects, saving both time and budget, click here.