Category: News

AMALIA 24.1 releases with support for 12nm FinFET alongside major enhancements to its Circuit Porting and Technology Analyzer tools

by Syed AhmadNewsPress Release

Thalia, a leader in analog, mixed signal and RF IP design migration, today announced the release of AMALIA 24.1. This latest version of the company’s efficient IP reuse and migration platform includes the recently announced support for 12nm FinFET technology and Circuit Porting simulation comparisons. Also introduced in this update is a summary report within AMALIA’s Technology Analyzer software. Using this report, key decision makers can quickly access the critical information they need to choose the right process technology nodes and optimum devices, streamlining the decision-making process.

“Integrating support for 12nm FinFET technology into AMALIA was an important step forward in ensuring our customers have the capabilities needed to use advanced process technologies,” explained Syed Ahmad, VP of Product Development at Thalia. “FinFET technology is crucial for developing semiconductor devices that are not only smaller, more efficient, and more powerful but also designed to meet the stringent requirements of advanced technology nodes. This enables their use in a wide range of applications, from consumer electronics and automotive systems to the Internet of Things.”

In addition to the support for 12nm FinFET technology, AMALIA 24.1 offers simulation comparison capability within its Circuit Porting tool. With this feature included, IP designers can not only port designs to new process nodes, they can also simulate and compare the outcomes of the original and ported designs, using their preferred simulator tool and see if any further adjustments are needed. This reduces the requirement for multiple iterations and saves design porting time.

A new feature included within the AMALIA 24.1 release is a report that provides a summary of the in-depth results from AMALIA’s Technology Analyzer findings.

“This latest enhancement to our software suite uses AI to provide a concise summary of key findings and recommendations taken from the standard report which, due to its comprehensive nature, can be hundreds of pages long. This drastically reduces the subsequent analysis time by providing the most relevant and critical information in a format that is quick and easy for senior designers and key decision makers to understand and make informed decisions,” Syed Ahmad explains.

The release of AMALIA 24.1 reflects Thalia’s dedication to supporting the semiconductor industry’s evolving needs, by not only maintaining up-to-date technology support but also by innovating and enhancing the user experience through new features that simplify complex processes.

For more information on how AMALIA 24.1 can facilitate your IP migration and optimization projects, saving both time and budget, click here.

Thalia’s CEO, Sowmyan Rajagopalan, speaks to Design & Reuse’s Gabriele Saucier at IP-SoC Grenoble 2023

by Sowmyan RajagopalanNews

In this video, we bring you an exclusive interview from IP-SoC Grenoble 2023, where Thalia’s CEO, Sowmyan Rajagopalan explores the latest company news and milestones from Thalia:

  • Thalia’s growth journey over the last six months
  • The latest AMALIA platform updates including qualification for 12nm FinFET and integration with additional leading EDA tools
  • Insight into the evolving market demands for analog IP migration 
  • Thalia’s future expansion plans and upcoming AMALIA platform developments

Interested in finding our more about Thalia’s AMALIA platform?

AMALIA enables customers to capitalize on the latest in advanced process technology and accelerate time to market for new products without compromising on cost and resource efficiency. It also enables them to speed up their product development cycles, while staying on budget and remaining efficient operationally. 

Find out more about AMALIA.

Hands-free driving – and the technology behind it

by Sowmyan RajagopalanBlogNews

Hands-free driving could be legal on UK roads by spring next year, the UK government has said. A consultation on the technology involved is under way. Specifically the UK’s Department for Transport (DfT) has issued a call for evidence into automated lane keeping systems (ALKS).

The technology to do this is still very much developing, although we can certainly expect that it will make significant demands on the semiconductor industry that Thalia serves. But first some background.

This consultation looks at level three (of five) on the way to the ultimate aim of completely automated driving. In stage two the vehicle can control both steering and acceleration / deceleration. The automation isn’t classed as self-driving because a human is still required to sit in the driver’s seat and be prepared to take control of the car at any time.

Level 3 vehicles, however, have what are called environmental detection capabilities and can make informed decisions for themselves, such as accelerating past a slow-moving vehicle. The driver must remain alert and ready to take control if the system is unable to execute the task but, in theory, the driver could do other things such as check email or even watch a movie – until the car prompts him or her to take over again.

But don’t get too excited just yet. The UK government’s call for evidence, at some 46 pages, makes some pretty stern safety demands of what it calls ‘a traffic jam chauffeur technology designed to control the lateral and longitudinal movement of the vehicle for an extended period without further driver command’. These demands include a driver availability recognition system, reasonable thresholds designed to prevent unintentional inputs into the override capabilities, a data storage system for automated driving and numerous compliance requirements involving monitoring and control criteria – to name but a few.

But that isn’t all. The ALKS regulation approved in June 2020 by the United Nations Economic Commission is for a system (in its current form) capable of operating at speeds of up to just 37mph. It is therefore designed for situations of heavy, slow-moving traffic on a motorway. Why motorways? Because they go one way and are more controlled and simpler environments than most others. A slow-moving motorway is a good place to try out stage three ALKS.

Elsewhere in Europe, Germany has drafted legislation for level 4 autonomous vehicles. As yet, the legislation remains unpublished, but Germany, as the country of origin for most OEMs relating to the technology behind assisted and self-driving vehicles, could expect to see the reality of self-driving vehicles sooner rather than later. If this is the case, German legislation will likely guide all other nations legislative developments.

Even with the restrictions at levels 3 and 4 of automation, the market seems to be a promising one. According to a report released earlier this year by Acumen Research and Consulting, the global automotive lane keep assist system market is expected to reach a market value of around US$7 billion by 2026 and is anticipated to grow at a CAGR of around 16% in terms of revenue during the report’s forecast period 2019 to 2026.

It will no doubt mean a lot of work supplying a whole new market with tech – and a whole new semiconductor market with relevant IPs. And, of course, this market has a lot of development to do; new requirements, new sensors, new software and new hardware will supersede each other. Within a lot less than ten years, we may see not only level four (vehicles operating in self-driving mode within a limited area) but early level 5 cars: able to go anywhere and do anything that an experienced human driver can do.

As for public acceptance of ALKS, we can certainly assume that even hiccoughs or bad publicity will only slow rather than stop the rollout of this form of automated driving, and that when the first completely autonomous cars arrive – sometime after 2026 in all likelihood – a $7 billion market will just be the start.

Design Considerations

by Rodger SykesBlogNews

Let’s say that a company buys into our IP reuse proposition. What is the best use of our technology in relation to its portfolio?

First and foremost the market defines everything. Every semiconductor company that designs more than one ASIC has to choose whether to build the portfolio or design new IPs. There are many factors that could potentially impact a decision but from a market point of view it’s all about the revenues these IPs or ASICs could generate – and that is about what the market wants and will pay for and a company’s relationship with its customers.

If an IP that a company builds in a new technology can generate a reasonable amount of money, then the number of licenses or units it sells before it recovers the cost could justify the work.

That in turn is driven by the number of resources required. Should third party help be sought.

What about opportunity cost? Does one choice completely negate another?

You might think that Thalia can impact every one of these considerations. You would be wrong. But there is still a lot we can do.

The cost to redevelop an analog or mixed signal complex IP block can be between half a million to a million Euros, that raises some obvious questions. Can enough licenses be sold to justify the outlay and make a profit? But if the cost to get that IP in silicon validated came down by up to 50%, that’s a game changer. That is something we might be able to help with. Our focus on targeted automation – which we are constantly evolving and improving – means we are able to reduce the design cycle time and hence the cost.

What about resources? How can a company identify them and bring them on board? If a third party–like Thalia – can do that, it might speed up the process and save money.

Opportunity cost, meanwhile, doesn’t need to be either/or. If you have your IPs in different nodes and technologies you don’t need to think in such absolute terms.

A company can look at all of these factors and choose a vendor, though first ensuring that the vendor can scale up to meet its requirements and do so reliably. And if that’s something you are considering, don’t forget to check the vendor’s bona fides and its reputation too. Has it ever promised more than it can deliver?

We have not. We understand our skillsets, the focus of our expertise and t the technologies we work with (though we are constantly evolving on all fronts). We also know that, if the time, place and customer needs fit our offering, then a shorter design cycle in a shorter time – and thus lower costs – are part of our USP.

Layout automation: achievable or illusory?

by Sowmyan RajagopalanBlogNews

We are extremely successful efficiently migrating, refining and optimizing existing IP for new technologies and applications. Specifically, we are able to reduce the number of iterations it takes to get from our starting point – analysis of the process technology – all the way to layout migration.

However, layout migration is one step that remains very challenging and it’s worth taking a little time explaining why it remains resistant to automation.

Firstly, layout migration is never uniform: it’s almost by definition a custom design process, in fact. If you move from, say, one semiconductor platform to another or from 40 nanometre to 28 nanometre, it’s not just the names and numbers that change – the chip’s characteristics also change.

The layout needs to factor in those aspects: the way the devices are placed, the metals, the routing, how the chip is configured. But that’s not all. The way you position or place the structures on the layout is also going to have an impact on circuit characteristics. So too is the size of nodes.

Essentially then, the size of the chip is dependent on how you put together the layout – and the factors you are dealing with are not uniform.

Design simulation is also affected. Schematic-level simulations and layout simulations were once comparable. Now they are diverging – mainly because there are various elements that schematic-level models cannot factor in.

Capacitance is another issue. There are fancy equations to explain this but, put very simply, it’s about ever smaller conductor-to-conductor spacing and the knock-on effect of parasitic capacitance, which impacts the frequency ranges and the circuit characteristics. Parasitics in these ever-smaller dimensions have become a big issue.

All of which explains why full-on layout automation is so challenging: it needs to address all the problems layout design can throw up. The reality is it can’t.

But that’s no reason to abandon automation entirely. Our IP re-use platform tool – AMALIA – does not generate a complete layout factoring in all circuit characteristics, device sizes and parasitics. For the moment, that is impossible.

However, generating a base framework that compares with the base design in aspect ratio, device placement and routing of main signal nodes will assist the layout designer with a good starting point. About 20-25 per cent of the layout work should be speeded up when we reach this point. This should happen in the next 12 months.

The goal is to have something that builds a basic framework of the layout. And if you can offer that you will reduce the amount of time a layout designer would have to spend then putting together the layout.

Thus our aim is targeted automation – and that is achievable. What isn’t achievable – and may never be – is an all-singing, all-dancing layout automation tool. If someone offers you that, be very, very wary.

Wi-Fi 6: new challenges – and an adaptable process

by Sowmyan RajagopalanBlogNews

The new wave of wireless is here. Known as Wi-Fi 6 (or, less thrillingly, 802.11ax), it delivers four times faster average throughput compared to Wi-Fi 5 with greater than 5 Gb/s data rate capability. That’s a maximum of 9.6 Gbps – theoretical, of course, though the headline rates are still impressive.

Wi-Fi 6 also supports a much larger volume of mobile devices in dense deployment environments (large public spaces like arenas and airports), and it does so more efficiently. If multiple end users (including IoT end users – that is, things as well as people) are being served in a busy environment, Wi-Fi will be able to cope a lot better than its predecessors – and with less drain on batteries or diminishing of battery life.

Wi-Fi 6, as one commentator puts it, couples the freedom and high speed of gigabit ethernet wireless with the reliability and predictability of licensed radio, not least thanks to its use of the channel access mechanism known as orthogonal frequency division multiple access (OFDMA).

It’s the latest innovation from the Wi-Fi Alliance, the industry organisation that since its formation in 1999, has grown with the technology to become a major driver of new Wi-Fi applications and products.

Wi-Fi is one of the most widely implemented and deployed technologies ever invented – and the new iteration shows every sign of continuing that trend. But despite the ubiquity of Wi-Fi, designing RF, analog and mixed signal blocks for Wi-Fi remains a challenge for the engineer – and it isn’t going to go away with the arrival of Wi-Fi 6.

For example, at some point will be required to take this specific version of Wi-Fi 6 and move it from one manufacturing process to another, if a customer so desires, to help that customer lower cost, reduce power consumption, improve performance or enhance manufacturing flexibility, for example.

Let’s be clear about this: we’re not moving from Wi-Fi 4 or Wi-Fi 5 to Wi-Fi 6. That would be an architecture change. This is about shifting manufacturing processes coupled with design improvement – within the technology.

Will dealing with Wi-Fi 6 mean that our work process becomes slightly more expensive or takes more time than before? Perhaps. But it will still be cost-effective, and thus the whole point of analog IP reuse will still be valid.

But, like Wi-Fi, we are constantly improving. We have been able to reduce the number of iterations it takes to get from our starting point all the way to eventual layout migration – and we are continuing that improvement process. We also have a lot of relevant experience to draw on and build on, most notably in dual band Wi-Fi and Bluetooth. This will help us to help our customers to find the cost-effective approach they need, which is our aim in every job we take on – even when it involves a brand-new evolution of Wi-Fi.

We are aware that Wi-Fi 6 will offer new challenges. But the process we will be applying is one in which we are well versed and which can be adapted to this new wave of wireless – if you have the skill and the experience. And we have both.

Presenting in a virtual world

by Sowmyan RajagopalanBlogNewsNews & Events

A few weeks ago, our founder and CTO, Sowmyan Rajagopalan, was due to give a presentation at the DATE Grenoble Conference. For obvious reasons, that conference didn’t proceed as planned, with speakers instead giving virtual presentations to the audience remotely.

Sowmyan gave the following presentation, talking about why analog IP reuse is a big problem for semiconductor companies, as well as providing an introduction of who Thalia is and how we can help.

His presentation addresses the decision fork that companies face: designing new IPs or building a portfolio of analog IPs.

Thankfully, this isn’t necessarily an either or situation though. We can help.

Watch his presentation to hear more.

Design Reuse – Design Migration

by Sowmyan RajagopalanNews

Thalia Design Automation partnering with In2fab have deployed their toolset targeting Design migration at an European Design House. The technology was used to migrate a large design across technologies, validate and centre the design.

Overall design cycle was reduced to 1/3rd of conventional migration methodology.

Analog Analyzer and Optimizer – Design Engagement

by Sowmyan RajagopalanNews

Thalia Design Automation’s AMALIA toolset – Analog Analyzer and Optimizer is now ready for design services engagement with Analog and Mixed signal design houses.
The tool incorporates innovative algorithms and CAD methodologies to quickly explore a large search space and find solutions that meet or better circuit requirements.