Chiplets and IP reuse made easy: Smaller node ASICs are not always the best way forward

Chiplets are a relatively new trend in helping designers of large complex system design to enable a cost-effectively modular approach to designing with costly SoCs. I say relatively because proposals started back in 2016 when DARPA used it as part of its CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program.

To quote DARPA, “The monolithic nature of state-of-the-art SoCs is not always acceptable for Department of Defense (DoD) or other low-volume applications due to factors such as high initial prototype costs and requirements for alternative material sets.”

If you look at the economics of SoCs it’s easy to understand why chiplets are of increasing interest to a wide range of system designers – not just the likes of DARPA: moving from a 45 nm process to a 16 nm process more than doubles the cost/mm². Migrate again to a 7 nm process and costs / mm² double again – that’s 4x the cost per yielded mm².

Chiplets do sacrifice some space (around 10 percent) for the ‘chiplet architecture’ – i.e. the chip interconnects, but the overall benefits of chiplets on total system costs is substantial.

The fundamental benefits of a chiplet approach are: low cost and easy way to repurpose the design and enable variants, with some die-to-die interconnect, a range of third party chips can be combined into a package. One of the most important contributing factors enabling the chiplet approach to system level design is today’s advanced packaging technologies.

Many of the benefits and how chiplet design works may sound rather familiar because it’s what Thalia Design and others in the IP Reuse industry have been enabling for decades. In fact, we see huge potential in chiplets and, done correctly, a strategy of reusable chiplets will present enormous time and cost savings. Time to market, ease of design / migration to new processes, familiarity with the design…all of the benefits Thalia’s AMALIA (TM) IP Reuse platform enables.

When approaching the chiplet design, you can create a portfolio of IP for dedicated functions, even before committing the design to silicon. This makes your chiplet design both technology-agnostic and fab-agnostic.

Thalia’s AMALIA Circuit and IP reuse platform gives you that flexibility. Thalia methodology ports your existing chiplets to new technology nodes or fabs in the shortest possible time.

Commercial considerations can be taken into account during the implementation. For example, if the final solution needs to use a specific foundry, for strategical reasons, the chiplets can be quickly and easily ported to that specific foundry and even technology node.

That raises the levels of flexibility in complex system-level implementations and also gives customers the maximum flexibility in defining their system-in-package solution.

The AMALIA platform only needs the chiplet source technology database and PDK, plus the target technology PDK. AMALIA can also help to create a complete chiplet portfolio. Thalia IP reuse suite of products can handle the complete design, reuse or migration of the chiplet in practically every fab or technology node.

Thalia’s partner network also provides the productization of chiplets in specific foundries, down to 7nm technology nodes.

If you are planning your own chiplet strategy, get in touch with us to find out how AMALIA platform can help to further simplify the IP reuse.