Rapid Tier1 to Tier2 migration analysis for 13 PMIPs facilitates second sourcing approach
Thalia’s partnership with a leading IP company to evaluate the potential migration of 13 Power Management IPs (PMIPs) from Tier1 to Tier2 40nm CMOS technology has set new benchmarks.
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Analyzing Process Technology for 40nm to 22nm RF Transceiver IP Migration
Thalia successfully helped a leading fabless semiconductor company assess the viability of migrating their RF Transceiver IP from 40nm to 22nm in just four weeks.
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Extending the life of a core security image IC
Thalia helped a manufacturer of high-quality image processing camera modules to migrate a circuit to upgrade a readout IC from its existing 350 nm process to 180 nm.
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Migration of a Whisper Trigger Amplifier
Rapid migration with Thalia Design Enabler reduces customer’s power requirements and retains design slot.
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Design centring of a reference voltage
Design-centring automation and expert design time savings while minimising area with the AMALIA platform.
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Migrating the design of a PLL to a 28nm process node
Thalia migrated a PLL to a 28nm node within a very tight time schedule due to the customer’s market demands.
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Technology Analyzer Case Study
Thalia deployed its Technology Analyzer to migrate a whisper trigger amplifier to a 22nm process with a tight deadline and key characteristics to be addressed.
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Comparing Characteristics: IP reuse and the role of the Technology Analyzer
New or reused IP? In-house or third party? Targeted or total automation? The right choices can save time and money.
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ADC migration case study
Thalia deployed targeted automation and expert design resources to speed schematic porting and block level design tuning with its AMALIA platform
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IPSoC Santa Clara 2019: Is efficient Analog IP reuse a myth? An innovative Approach to make Analog IP reuse a reality
Is efficient Analog IP reuse a myth? An innovative Approach to make Analog IP reuse a reality.
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Analog schematic porting
Fast and efficient schematic porting was a key step when Thalia was asked to migrate a customer’s Bluetooth design from a 28nm to 40nm process node
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CDNLive: Analog IP reuse & process migration: challenges & an innovative methodology to address them
Presentation by Thalia CTO and Founder Sowmyan Rajagopalan, delivered at CDNLive Europe 2018
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