Category: News & Events

Semiengineering.com recently reported on an industry survey showing an increase in respins due to analog circuitry failing or falling out of operable range.

The reasons behind this trend are complex, but the article suggests it comes down to analog tuning – the process of tweaking a design to maximise performance while staying within the operational parameters of the overall circuit. The article also explains that the chief scientist at Mentor, a Siemens Business, analysed the results to determine the scale and scope of this trend – whether it was affecting newer designs on the latest technology nodes, or if it was a universal problem.

Figure 1: Flaws contributing to ASIC re-spins. Source: Wilson Research and Mentor, a Siemens Business

It would be easy to assume that the problem was relating to newer nodes and newer processes, but on review, the issues are affecting technology nodes from sub-7nm to 150nm and higher.

Figure 2: Tuning analog circuit flaws by design size. Source: Wilson Research and Mentor, a Siemens Business

So what’s causing the increase in failures?

Put simply, the complexity of new devices. The number of complex devices is growing, and is set to continue with the expansion of the IoT. Automotive components are also massively on the rise, both in number and complexity, thanks to the developments towards self-driving cars. Companies are trying to fit all circuitry on the same substrate or on a single technology node and schematic simulation isn’t able to accurately assess function and full parameters.

Fig 3: Defect rates for automotive ICs and causes of failures. Source: Mentor, a Siemens Business

There will always be issues arising when working with new nodes and there is a learning curve for design teams to fully come to terms with the limitations, issues and particular traits displayed by these new nodes. Implementing this knowledge into toolsets is only achievable once they are fully understood. But if that learning curve therefore involves respins and ‘back to the drawing board’ moments at increasing frequency, then time to market will be affected for new devices. And increasing time to market for a new chip in a competitive industry can be the difference between market success and failure. Second place really is the first loser.

As IP reuse specialists, this is not news to us. We have worked with many clients evolving analog IP from one technology to another or even from one foundry to another. Most engagements are accompanied with the need to improve power consumption, speed, performance or the physical size of the silicon chip, and when these needs are implemented, they have knock on effects to other characteristics, resulting in the silicon not performing to specification.

We know this; it’s what we do. It’s why we developed our technology analyzer to be able to identify differences between base and target technologies and highlight where a circuit will fail. Our Trifecta, including the AMALIA platform, helps to identify the root cause of an issue and allows our design engineers to nudge a design back into specification before migration; mitigating the need for respins for out-of-tolerance circuits.

As experts in reusing analog IP on different process nodes or technologies, we’ve spent years developing processes to ensure IP works as expected and as needed in target technologies. We do this by deploying our Trifecta – advanced development methodologies, the targeted automation of our AMALIA platform and our design expertise. Using this Trifecta approach means we can verify IPs and their behaviour or performance before migration. Part of the AMALIA platform uses our proprietary technology analyzer to rapidly identify parameters in both base and target technologies to identify issues, allowing our expert designers to tweak characteristics and knock the design into specification.

This methodology, used by us across multiple technology nodes and foundries, has the potential to play a significant role in the fast and efficient migrating of analog IP for the ever-increasing number of IoT, mobile and handheld devices. Analog components sit alongside digital and ensuring everything functions as it should is key in getting new products to market ahead of the competition.

The new wave of wireless is here. Known as Wi-Fi 6 (or, less thrillingly, 802.11ax), it delivers four times faster average throughput compared to Wi-Fi 5 with greater than 5 Gb/s data rate capability. That’s a maximum of 9.6 Gbps – theoretical, of course, though the headline rates are still impressive.

Wi-Fi 6 also supports a much larger volume of mobile devices in dense deployment environments (large public spaces like arenas and airports), and it does so more efficiently. If multiple end users (including IoT end users – that is, things as well as people) are being served in a busy environment, Wi-Fi will be able to cope a lot better than its predecessors – and with less drain on batteries or diminishing of battery life.

Wi-Fi 6, as one commentator puts it, couples the freedom and high speed of gigabit ethernet wireless with the reliability and predictability of licensed radio, not least thanks to its use of the channel access mechanism known as orthogonal frequency division multiple access (OFDMA).

It’s the latest innovation from the Wi-Fi Alliance, the industry organisation that since its formation in 1999, has grown with the technology to become a major driver of new Wi-Fi applications and products.

Wi-Fi is one of the most widely implemented and deployed technologies ever invented – and the new iteration shows every sign of continuing that trend. But despite the ubiquity of Wi-Fi, designing RF, analog and mixed signal blocks for Wi-Fi remains a challenge for the engineer – and it isn’t going to go away with the arrival of Wi-Fi 6.

For example, at some point will be required to take this specific version of Wi-Fi 6 and move it from one manufacturing process to another, if a customer so desires, to help that customer lower cost, reduce power consumption, improve performance or enhance manufacturing flexibility, for example.

Let’s be clear about this: we’re not moving from Wi-Fi 4 or Wi-Fi 5 to Wi-Fi 6. That would be an architecture change. This is about shifting manufacturing processes coupled with design improvement – within the technology.

Will dealing with Wi-Fi 6 mean that our work process becomes slightly more expensive or takes more time than before? Perhaps. But it will still be cost-effective, and thus the whole point of analog IP reuse will still be valid.

But, like Wi-Fi, we are constantly improving. We have been able to reduce the number of iterations it takes to get from our starting point all the way to eventual layout migration – and we are continuing that improvement process. We also have a lot of relevant experience to draw on and build on, most notably in dual band Wi-Fi and Bluetooth. This will help us to help our customers to find the cost-effective approach they need, which is our aim in every job we take on – even when it involves a brand-new evolution of Wi-Fi.

We are aware that Wi-Fi 6 will offer new challenges. But the process we will be applying is one in which we are well versed and which can be adapted to this new wave of wireless – if you have the skill and the experience. And we have both.

These are strange times. Usually face-to-face meetings and conferences are how we catch the pulse of our industry, pick up on trends and opportunities. Without them, these days we need to rely on our experience and listen even more carefully to what customers are telling us to better anticipate and meet their needs.

But even now the direction of travel can be discerned from the themes that dominated at the virtual edition of the DATE conference I took put in last month and those that dominated the most recent IP SoC conference back in December (which feels like a lifetime ago!).

I think it’s true to say that I’m not sure that in either case I could point to genuinely new themes – rather the consolidation and impending commercialization of prospects that have been around for some time.

It’s fair to say we are still a long way from peak autonomous car, certainly as far as trade shows and the press are concerned. The emphasis in Grenoble was around safety and security. From our point of view, we feel our solution can make important contributions to improving cost and time-to-market for a sector that will undoubtedly need to port a wide range of technologies and process nodes. For example, LIDAR systems currently employ costly multitudes of ICs. For the industry to scale – and to realise the $173 billion market value predicted for 2040 – will require timely, cost effective and highly integrated ADCs. This is a demand that pretty much defines the Thalia value proposition.

Yet in Grenoble, as elsewhere over the past 12 months, the overarching theme linking pretty much everything remained 5G (and, of course, autonomous vehicles are currently a strongly touted 5G use case).

After a few tough years, the steady rollout (especially in the US and Asia) of commercial 5G networks makes the semiconductor industry feel a little better about itself. The sense is that new networks based around the new radio are likely to accelerate the currently sluggish smartphone refreshment-cycle. Both Gartner and IDC predict a slight uptick in new smartphone sales in 2020 and agree 5G will be the driver.

The focus on smartphone sales is understandable but, as we have suggested elsewhere, even if a relatively limited range of the many use cases conjured to validate 5G investments come to fruition, the 5G semiconductor opportunity extends way beyond handsets. If vision becomes reality, 5G will become a cornerstone of the full digital platform. This will mark an era in which connectivity and advanced functionality will become part of every conceivable product – from trucks, trains and shipping containers to vending machines and lighting infrastructure.

Which implies a potentially exciting moment for the industry. But the to-do list that needs to be addressed to make all this happen remains fairly lengthy. And some line items are pretty basic. For example, at a network level, to get beyond current consumer data usage applications, there is an urgent need to define core base station product configurations to suit different deployment scenarios. From residential to urban, and from all-in-one to highly disaggregated and virtualized, many physical types of cell will be required to meet all the many requirements of 5G. However, this risks fragmentation, which demands establishing some baseline specifications for each major category of cell, allowing for large scale to be achieved, while leaving individual chip and system vendors the flexibility to differentiate within those frameworks.

Yet despite the challenges, the opportunity is there and Europe’s semiconductor industry needs to leverage its considerable experience and reputation for innovation to make the most of it. To this end, several presenters in Grenoble highlighted Europe’s leadership role in the development of Radio Frequency Silicon-on-Insulator (RF SOI) platforms, based on both PD-SOI and FD-SOI. RF SOI chips are used in the RF switches which help to manage a smartphone’s transmit/receive functions. As 5G evolves, PD-SOI and FD-SOI are set to become extremely important technologies , not least as potential standards for future 5G-mmWave handsets, base stations and small cells IoT. They are also recognized as enablers for new RF domains for sensors and connectivity beyond 5G.

The advantages of FD-SOI in particular are well rehearsed, delivering improved speed, reduced power and a significantly simplified manufacturing process. As I mentioned in a recent blog [add link], this attractive power/performance/cost trade-off is leading growing numbers of clients to make SOI part of their product roadmaps. In the context of the complex service/product/technology evolutions underpinning the 5G Era, SOI is already finding favour in the automotive industry (reduced cost coupled with radiation tolerance are key factors here, while strong RF and analogue performance will ensure it has an important role to play in the role out of IoT products and infrastructure.

The good news is that the home of SOI innovation is in Europe – in Grenoble, in fact, led by key players like Soitec, STMicroelectronics, CEA Leti and Dolphin who are demonstrating the potential of the RF-SOI and FD-SOI design platform to drive the development of fast growing markets like automotive, IoT and aerospace. As a member of the SOI Consortium, Thalia is committed to playing a significant role in this European ecosystem and we have already demonstrated our ability to accelerate the deployment of IP and SoC design into FD-SOI.

Here’s a link to the virtual presentation I gave at the DATE conference.

And see below my video interview with Gabrielle Saucier of Design & Reuse.

Looking back over the last 18 months, there has been a rapid uptake of fully-depleted silicon-on-insulator (FD-SOI) process technologies. With production at foundries such as GlobalFoundries and Samsung now in full swing, more and more analog designers are reaping the benefits of FD-SOI.

At Thalia we’ve been at the forefront of some of these changes, having worked with multiple customer on projects that use FD-SOI technology.

Given that we are now effectively prevented from going to meet with clients and prospects, I thought that now would be a good time to take a look at some of the drivers behind this shift towards FD-SOI, and the benefits and challenges it can bring for the analog designer.

Figure 1 contrasts the structures of traditional bulk planar and SOI type transistors. The main difference is the inclusion of a buried oxide layer that isolates the channel of the transistor from the bulk silicon of the substrate. This results in a very thin, controllable channel structure, with much lower leakage currents being ‘lost’ into the device substrate than traditional alternatives.

This in turn improves two key figures of merit for the device. First, standby power consumption is dramatically reduced. Second, the threshold voltage is much more predictable and controllable – yields are improved, and power/performance tradeoffs via voltage scaling are more easily enabled.

The penalty is that FD-SOI transistors are generally not so fast. But one other feature of the technology – particularly important for mixed signal and analog designs – allows smart designers to mitigate this effect. Biasing the body structure at a different voltage to the source enables the designer to trade speed for power: a reverse bias increases the threshold voltage of the device, making it slower, but reducing leakage current; conversely, forward biasing reduces the threshold voltage, increasing the speed of the device, at the cost of power.

Thalia has worked on a number of projects that utilize SOI technologies. A recent RF front end for Bluetooth Low Energy (BLE), for example, used exactly the techniques I have outlined above. We migrated an entire subsystem design, composed of around 30 blocks (including ADCs, PLLs, mixers, amplifiers and power controllers), to a 28nm Samsung FD-SOI process.

The circuit was verified for compliance with design specifications. Design changes were implemented to ‘nudge’ the design to meet the requirements. And we made full use of the body biasing techniques I have already outlined. We used reverse body biasing to keep leakage as low as possible in parts of the circuit in which speed was not a factor; and, where speed was a key requirement, implemented forward gate biasing to increase performance.

We’re expecting increasing numbers of customers to start moving their analog and mixed signal designs to SOI technologies in the coming months and years. The process is not without its challenges: but with an intimate knowledge of circuit design and optimization, and of the subtleties of the processes themselves, there are substantial advantages to be reaped.