Category: Press Release

Thalia Design Automation announces AMALIA Platform release 25.3 qualified for advanced process nodes down to 4nm

by thaliadaeditorPress Release

Platform qualification for sub-10nm semiconductor processes enables tier-1 customers to address next-generation analog and mixed-signal designs with breakthrough intelligent auto-routing capabilities

Cwmbran, United Kingdom– 4th November 2025, – Thalia Design Automation, a leading innovator in electronic design automation (EDA) solutions, today announced the release of AMALIA Platform version 25.3, now qualified for advanced semiconductor process technologies down to 4nm. This milestone qualification enables the platform to support cutting-edge FinFET and advanced node designs, positioning Thalia as a critical solution provider for tier-1, fabless semiconductor companies and leading foundries developing next-generation products. The release also introduces groundbreaking intelligent auto-routing capabilities and enhanced device modeling tools that address critical challenges in process node migration and high-frequency circuit development.

Platform qualification for sub-10nm process technologies

The qualification of AMALIA Platform 25.3 for process nodes down to 4nm represents a strategic advancement for Thalia Design Automation, enabling the company to serve customers designing at the most advanced semiconductor process technologies available today. This capability is essential for analog and mixed-signal IP development in applications including 5G/6G communications, advanced automotive systems, artificial intelligence accelerators and high-performance computing platforms.

“Achieving qualification for 4nm process technology is a defining moment for Thalia Design Automation,” said Sowmyan Rajagopalan, CEO, Thalia. “This positions AMALIA as the only specialized full flow, analog and mixed-signal IC migration platform capable of addressing the extreme complexity and precision requirements of sub-10nm designs. Our customers can now leverage our intelligent automation capabilities across the full spectrum of modern semiconductor processes, from mature nodes to the most advanced technologies in production.”

The sub-10nm qualification enables AMALIA users to work with the advanced FinFET used by leading foundries. This capability is particularly critical for analog and RF circuit blocks that must be integrated into large system-on-chip (SoC) designs fabricated at advanced nodes.

Breakthrough intelligent auto-routing algorithm

The centerpiece of AMALIA Platform 25.3 is a revolutionary auto-routing algorithm integrated with Layout versus Layout (LVL) comparison capabilities. This intelligent system automatically resolves open and short circuit issues that commonly occur during layout migration between different process design kits (PDKs), dramatically reducing manual intervention and design cycle time.

“The development of this intelligent auto-routing capability represents a fundamental advancement in layout automation,” said Awadh Pandey, Thalia’s Director of Engineering. “Our algorithm doesn’t just identify connectivity issues – it intelligently resolves them by finding optimal routing paths while avoiding design rule violations and maintaining signal integrity.”

The auto-routing system addresses the common challenge where P-cell size changes during PDK migration cause connectivity disruptions. Traditional approaches require manual intervention to reconnect nets, a process that can take weeks for complex analog blocks. The AMALIA 25.3 solution automatically recognizes disconnected nets, identifies the optimal reconnection strategy, and implements the routing while avoiding shorts with adjacent metal layers.

Real-world validation and efficiency gains

The auto-routing development was driven by real-world customer challenges, including a complex bandgap reference design migration that previously required four weeks of manual layout engineering effort. With AMALIA 25.3’s intelligent auto-routing, similar migrations can be completed with minimal manual intervention, delivering efficiency improvements of 75% or more compared to traditional manual approaches.

Advanced ‘Safe Operating Area’ analysis

AMALIA Platform 25.3 introduces comprehensive Safe Operating Area (SOA) analysis capabilities within the Technology Analyzer module. This feature extracts critical device reliability parameters directly from PDK model files, including maximum drain-to-gate, gate-to-source, and bulk-to-drain voltages. The SOA data is automatically incorporated into summary reports, providing designers with essential reliability information for robust circuit design.

Enhanced ‘Smart Mapping Generator’

The release includes significant enhancements to the Smart Mapping File Generator, creating seamless compatibility between Technology Analyzer and Circuit Porting modules. The new system eliminates the need for manual parameter modifications, generating mapping files that work directly across both tools. Additionally, a template-based approach now supports custom device integration, allowing companies with proprietary device libraries to easily incorporate their components into the AMALIA workflow.

Strategic market impact

The AMALIA Platform 25.3 qualification for sub 10nm process technology, combined with its advanced feature set, directly addresses the critical needs of:

  • Tier-1 fabless semiconductor companies: Enabling analog and mixed-signal IP development at advanced nodes for integration into next-generation SoCs, with automated solutions for complex layout migrations across multiple process technologies
  • Integrated device manufacturers (IDMs): Providing comprehensive analysis tools and automation tools for in-house IC development spanning mature to advanced process nodes
  • Leading-edge CMOS semiconductor foundries: Supporting sub 10nm process technologies, enabling enhanced design rule checking, migration support, and analog IP qualification
  • Analog, mixed-signal, and RF IC design teams: Delivering specialized automation tools that understand the unique challenges of non-digital circuit design at both advanced and mature process nodesHigh-frequency modeling capabilities

High-frequency modeling capabilities

Building on previous releases, AMALIA Platform 25.3 continues to advance high-frequency modeling capabilities, supporting the demanding requirements of RF and high-speed analog applications. These enhancements enable accurate simulation and analysis of next-generation wireless, automotive radar, and high-performance computing designs.

Customer engagement and market validation

The platform’s Smart Mapping Generator capabilities have been demonstrated to a major foundry partner, validating the approach for large-scale manufacturing environments. The auto-routing algorithm represents an entirely new capability class, developed through intensive collaboration with layout engineering teams to understand real-world migration challenges.

Availability and technical specifications

AMALIA Platform 25.3 will be available to customers from end of October 2025, with full technical documentation and support. The release includes comprehensive APIs for integration with existing design flows and extensive customization options for company-specific requirements.

About Thalia Design Automation

Thalia is a leading provider of analog, mixed-signal and RF IP design migration solutions. The company’s AMALIA Platform harnesses advanced automation and AI/ML technology to streamline the migration process, enabling semiconductor companies to reduce time, cost and complexity while optimizing their ability to create innovative applications. Thalia serves customers worldwide across automotive, communications, consumer electronics and industrial markets.

Thalia Design Automation launches AMALIA Platform 25.2

by thaliadaeditorPress Release

Revolutionary AI-powered platform delivers advanced electromigration compliance and streamlined Key Devices integration

Cwmbran, United Kingdom – July 16, 2025 – Thalia Design Automation today announced the release of AMALIA 25.2, a groundbreaking evolution of its industry-leading analog and mixed-signal IP reuse platform.  This major release introduces the fully integrated Design Pre-Trained Transformer (DPT) AI engine, advanced electromigration compliance workflows, and strategically repositioned Key Devices identification that collectively transform the semiconductor design migration landscape.

AI engine integration transforms analog IC design migration

The Design Pre-Trained Transformer (DPT), first introduced earlier this year, now serves as the core AI engine powering the entire AMALIA Platform.  This sophisticated, pre-trained system enables AMALIA to be trained seamlessly to customer environments with different foundries and nodes enabling fine-tuning for specific design migration scenarios.  By intelligently analyzing both source design schematics, layouts and process design kits (PDKs), DPT extracts critical process and circuit features to drive smart migration decisions —dramatically accelerating the path for design migration.

Advanced electromigration compliance ensures reliability

AMALIA 25.2 introduces a powerful new electromigration compliance feature that automatically adjusts power and ground buses during layout porting.  Through sophisticated analysis of current density and sheet resistance, the system ensures migrated designs meet stringent EM constraints across advanced nodes, including FinFET technologies.  This capability significantly reduces the risk of failures in next-generation semiconductor designs while supporting an extensive range of process technologies.

A 'before' and 'after' screenshot of a section of layout fixed by Electro Migration feature
Electro Migration Fixer in AMALIA 25.2
The two screenshots illustrate the before and after for a small section of a migrated design.
For this illustration, the source and target design use a  generic PDK for a 90nm and 45nm process respectively.
The Current Density Source to Target is 2, i.e. the source technology supports twice the current for same metal width compared to the target technology.
After selecting a particular metal layer and running the Electro Migration Fixer feature AMALIA intelligently understands it needs to increase the metal width 2X and where required increase the number of vias.

Strategic Key Devices enhancement accelerates workflow

The enhanced Key Devices capability has been expanded and strategically repositioned from the Design Enabler module to the earlier Circuit Porting Pro module within the migration workflow.  This feature ensures performance-critical components are identified and preserved from the very beginning of the migration process, eliminating costly design iterations and maintaining design intent throughout the entire workflow.

Industry leadership in analog IP migration

“AMALIA 25.2 delivers breakthrough capabilities that can improve engineer throughput by an order of magnitude,” said Sowmyan Rajagopalan, CEO at Thalia Design Automation.  “Features like advanced inductor analysis, schematic migration with parasitic preservation, and intelligent metal stacking are true game changers.  As pioneers in analog migration, we’re continuously expanding our platform to support the increasingly complex demands of modern semiconductor design.”

The release underscores Thalia’s commitment to pushing the boundaries of semiconductor design automation, delivering solutions that address the increasingly complex challenges of advanced node migration while maintaining the precision and reliability that analog and mixed-signal designs demand.

About Thalia Design Automation

Since 2011, Thalia Design Automation has pioneered semiconductor IP design migration solutions, empowering industry leaders through innovative, bespoke approaches to analog, mixed-signal, and RF IC design migration.  The company continues to drive industry transformation through cutting-edge automation technologies that accelerate time-to-market while ensuring design integrity.

Media Contact: Pete Davy, Consultant,  Thalia Design Automation pete.davy@thalia-da.com

Thalia enhances AMALIA Platform with new AI models to revolutionize analog, RF and mixed-signal IC design migration

by thaliadaeditorPress Release

Cwmbran, United Kingdom – April 29, 2025 – Thalia, a cutting-edge semiconductor solutions provider, unveils the latest version of its AI-powered AMALIA Platform, offering advanced end-to-end IP reuse capabilities specially designed for semiconductor companies and silicon foundries.

The new release introduces significant enhancements to the automated device-stretching functionality within the Layout Automation Suite of AMALIA.   Noteworthy additions to the platform include substantial improvements to inductor characterization and accurate area estimation models, underscoring Thalia’s commitment to driving efficiency and reducing design migration time.

Awadh Pandey, Thalia’s Director of Engineering, highlighted the innovation behind these updates, stating, “Our engineers’ deep expertise in analog and RF IC design, combined with AI modeling proficiency, has enabled us to deliver time-saving user interactions in physical layout design. The refined inductor characterization and area estimation features will significantly cut down both time and costs associated with the IC design migration process.”

Figure – Illustration of automatic device stretching. Creating space, layers/metal/shapes automatically adjusted

New features in release version 25.1

  • Layout Automation Suite enhancements: Automatic device stretching, DRC detection and correction, and metal stacking features streamline layout optimization, ensuring compliance with design rules and enhancing connectivity.
  • Inductor characterization improvement: For RF applications like Wi-Fi and Bluetooth devices, the updated inductor characterization feature offers automated analysis based on PDK data, enhancing efficiency and accuracy for designers.
  • Enhanced area estimation model: Integrated into the Circuit Porting Suite, the updated model provides precise area estimates, enabling customers to optimize space utilization and improve design performance.

Customer benefits include

  • Increased efficiency:  Automation reduces manual effort, saving time for critical project aspects.
  • Enhanced accuracy:  Automatic error detection and correction ensure adherence to design rules, improving product quality.
  • Cost savings:  Efficient space use minimizes manufacturing costs and post-production revisions.
  • Customer satisfaction:  Tailored features address specific design challenges, providing a competitive edge in the market.

Video illustrations of new capabilities

A quick video which demonstrates automated device-stretching capability in AMALIA’s Layout Automation Suite

Thalia joins GlobalFoundries’ GlobalSolutions Ecosystem to advance IP reuse and design migration

by thaliadaeditorPress Release

Cwmbran, United Kingdom – 17th April 2025 – Thalia, a leading provider of analog, mixed-signal, and RF IP design migration solutions, is pleased to announce its partnership with GlobalFoundries (Nasdaq: GFS) (GF), a global leader in semiconductor manufacturing.  As a member of GF’s GlobalSolutions™ Ecosystem, Thalia brings its cutting-edge AMALIA Platform to a broader audience of GF customers, empowering them to tackle the challenges of design migration across a diverse range of technology nodes.

The AMALIA Platform harnesses advanced automation and AI/ML technology to streamline the migration process for analog, mixed-signal, and RF IPs.  With this innovative platform, GF customers can reduce the time, cost, and complexity associated with migration while optimizing their ability to create groundbreaking applications and expand their offerings in today’s fiercely competitive semiconductor market.

“Joining forces with GlobalFoundries marks an exciting milestone for Thalia,” said Sowmyan Rajagopalan, CEO, Thalia.  “This collaboration allows us to deliver unparalleled value to our shared customers, simplifying the complexities of analog design migration and IP reuse.  By providing the tools needed to diversify product offerings and adapt to global supply chain dynamics, we are helping customers stay ahead in an ever-evolving industry.”

Ziv Hammer, Senior Vice President of Design Platforms and Services at GlobalFoundries, commented: “Thalia’s proven expertise in analog and mixed-signal design, combined with GF’s advanced technologies, enables our customers to drive innovation more efficiently.  By leveraging AI/ML capabilities, they can accelerate their product development cycles and bring cutting-edge solutions to market faster.”

GF’s GlobalSolutions™ Ecosystem represents a collaborative network of leading design, IP, and OSAT providers that work closely with GF to deliver end-to-end semiconductor solutions.  By building on these strategic partnerships and GF’s industry-leading process technologies, the GlobalSolutions Ecosystem ensures tailored, high-performance solutions for customers across a wide range of critical industries.

About GlobalFoundries
GlobalFoundries (GF) is a leading manufacturer of essential semiconductors the world relies on to live, work and connect.  We innovate and partner with customers to deliver more power-efficient, high-performance products for the automotive, smart mobile devices, internet of things, communications infrastructure and other high-growth markets. With our global manufacturing footprint spanning the U.S., Europe, and Asia, GF is a trusted and reliable source for customers around the world.  Every day, our talented global team delivers results with an unyielding focus on security, longevity, and sustainability. For more information, visit gf.com

Thalia Announces Latest Version of AMALIA with Game-Changing ‘Device-Stretching’ Algorithm and Flip Well Intelligence

by thaliadaeditorPress Release

Cwmbran, United Kingdom – 11/02/2025 – Thalia Design Automation is thrilled to announce the immediate availability of the latest version of the AMALIA Suite, their AI-powered industry end-to-end IP reuse platform. 

This release brings significant enhancements throughout AMALIA, particularly within its Layout Automation Suite.  The solution retains the intrinsic value of production silicon, delivering the final step in the design migration flow.  It employs a custom AI Design Transformer engine for analog physical implementation, leveraging the source layout and PDK.  The migrated layout maintains the existing floorplan, ensuring DRC/LVS integrity.  With AMALIA, customers can have a dedicated solution to the challenge of analog and mixed-signal migration and reliably achieve migration design time savings of up to 40%. 

“Our mantra is to continually drive down migration design cycle time and we achieve this with dramatic steps at each major release of AMALIA,” said Thalia’s CEO, Sowmyan Rajagopalan.  “We’ve introduced a game-changer within the Layout Automation Suite with a new device-stretching algorithm, metal stacking, along with significant functionality enhancements to automate the identification and migration to Flip Well designs for FDSOI.”

IP layout migration from one silicon process to another often encounters challenges due to varying PCell sizes. This results in open and shorts when trying to maintain the floor plan between the source and target technology. Fixing this manually can be a very time consuming. AMALIA’s new ‘device-stretching’ algorithm solves this issue while preserving the floorplan, delivering DRC-clean results, and promising substantial time savings.

For designs migrating to or from FDSOI, new analysis capabilities in AMALIA’s Technology Analyzer solution can identify standard transistor versus Flip Well devices and their unique electrical connection requirements, This knowledge seamlessly carries through to the Circuit Porting phase of migration, where AMALIA efficiently guides the user with their relevant design options.

These new capabilities – the device stretching algorithm, metal stacking and the analysis for Flip Well devices – represent significant advances in AMALIA.Thalia’s customers have experienced design cycle time reductions of up to 40%, thanks to continuous advances in the tool suite.  This latest product release reinforces AMALIA’s unique position in analog design and IP migration.

For more information, visit thalia-da.com or contact us here.

Summary of capabilities added to AMALIA products in release 24.4

  • Layout Automation Suite
    • New device-stretching algorithm
    • Smart vias porting to achieve DRC-clean vias
    • Improved device mapping generator
    • Devices shifting based on layer combination
  • Design Enabler
    • Enhancements  to rapidly identify devices that impact circuit performance
  • Circuit Porting Suite
    • Flip well identification and related unique connections
    • Conditional device mapping and improved generator
    • Circuit area calculation
  • Technology Analyzer
    • Preference driven device mapping
    • Flip Well design recognition in FDSOI process technology
    • AI device recognition and analysis
    • Enhanced waveform interpolation algorithm
Figure 2 Layout Automation Suite GUI and AMALIA integration within Cadence Virtuoso

Disruptive AI-powered Layout Automation software launched as part of Thalia’s latest AMALIA platform release

by Syed AhmadPress Release

Thalia, a leader in analog, mixed signal and RF IP design migration, today announced the release of AMALIA 24.3 with the first preview of its AI-powered layout porting software, the fourth component available in the comprehensive IP reuse platform.

Customers can now benefit not only from the ground-breaking Technology Analyzer and Circuit Porting suite, as well as the Design Enabler (core), but also the Layout Automation (LA) software which is the final stage in the process of providing designs to the foundry.

The AMALIA LA software uses the source design’s layout as the starting point and this unique approach facilitates the software to maintain the floorplan placement and preserves all intelligence generated on the existing IP through silicon validation. This is then tied with DR checks to ensure the final layout is DRC clean.

Sou Bennani-McCord, VP of Sales at Thalia, said:

“Today is another milestone for Thalia as we introduce our final solution to complete the AMALIA flow allowing customers to take their existing IPs from process technology analysis, porting of schematics/test benches to verification including estimated parasitics, to migrating the layout in the target technology.

“What we have today is a complete end-to-end IP reuse/migration platform that is the most comprehensive on the market and offers our customers best-in-class IP reuse that is fast, cost-effective and accurate. We look forward to introducing the new LA tool to our existing customers this month before launching it to the broader market early next year.”

The AMALIA 24.3 release includes other improvements to the platform such as enabling Key Device Identification to assist with meeting key design specifications in the AMALIA Design Enabler. It also includes DesignSync version control supporting customers’ design workflow in AMALIA Circuit Porting.

AMALIA is Thalia’s comprehensive end-to-end IP reuse software platform. Leveraging automation and AI/ML capabilities, it drastically reduces the complexity, cost and time traditionally associated with migrating and optimizing existing applications. Customers can make use of a discrete component of the AMALIA platform or leverage the complete platform providing them flexibility in how to manage their design migration requirements.

To find out more about the AMALIA Layout Porting, or to try the AMALIA platform, visit www.thalia-da.com

Thalia’s AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%

by Syed AhmadPress Release

Thalia, a leader in analog, mixed signal and RF IP design migration, today announced the 24.2 release of its AMALIA platform. The latest update brings advanced features to the AMALIA toolset including estimated parasitics for enhanced design accuracy and a faster migration process for semiconductor IP design engineers.

AMALIA 24.2’s stand-out feature directly tackles one of the most intricate challenges in semiconductor design—accurate parasitic estimation. AMALIA eliminates this traditional constraint and streamlines the design process by intelligently incorporating extracted parasitics from the source design and including them in the circuit porting phase to provide estimated parasitics early in the design process. As a result, the accuracy of the ported schematic is improved, reducing the need for multiple post-layout parasitic extraction (PEX) iterations by at least 30%. This is particularly beneficial in high-frequency applications, and smaller process technology nodes, where precision and speed are paramount.

With this latest enhancement to the AMALIA platform, Thalia once again demonstrates its dedication to reducing design cycle times and associated costs, empowering businesses to achieve faster time-to-market for new product innovations. The new feature streamlines the schematic porting by removing the need for skilled designers to estimate parasitics manually, saving valuable resources and speeding up the design verification process.

Syed Ahmad, VP of Product Development at Thalia, remarked on the update, “With AMALIA 24.2, we’re not just updating a platform; we’re setting a new industry standard for efficiency and precision in IP migration. Estimated parasitics in AMALIA is a testament to our commitment to innovation and the tangible benefits it brings to our customers.”

In addition, AMALIA 24.2 enhances the IP migration experience with a new design centering assistant feature, and updates to its advanced device mapping. The design centering assistant quickly identifies critical devices that impact performance, facilitating precise adjustments, while the device mapping table now benefits from AI/ML-driven auto device recommendations, ensuring optimal device selection and removing the need for manual work.

The launch of AMALIA 24.2 is a pivotal moment for design engineers looking to navigate the complexities of semiconductor design migration with greater ease and accuracy. Thalia remains at the forefront of this endeavor, continuously seeking ways to refine and enhance the IP design migration process to deliver tangible value to businesses trying to maximize their team resources and productivity.

Find out how AMALIA 24.2 can facilitate your IP migration projects, saving both time and budget.

AMALIA 24.1 releases with support for 12nm FinFET alongside major enhancements to its Circuit Porting and Technology Analyzer tools

by Syed AhmadNewsPress Release

Thalia, a leader in analog, mixed signal and RF IP design migration, today announced the release of AMALIA 24.1. This latest version of the company’s efficient IP reuse and migration platform includes the recently announced support for 12nm FinFET technology and Circuit Porting simulation comparisons. Also introduced in this update is a summary report within AMALIA’s Technology Analyzer software. Using this report, key decision makers can quickly access the critical information they need to choose the right process technology nodes and optimum devices, streamlining the decision-making process.

“Integrating support for 12nm FinFET technology into AMALIA was an important step forward in ensuring our customers have the capabilities needed to use advanced process technologies,” explained Syed Ahmad, VP of Product Development at Thalia. “FinFET technology is crucial for developing semiconductor devices that are not only smaller, more efficient, and more powerful but also designed to meet the stringent requirements of advanced technology nodes. This enables their use in a wide range of applications, from consumer electronics and automotive systems to the Internet of Things.”

In addition to the support for 12nm FinFET technology, AMALIA 24.1 offers simulation comparison capability within its Circuit Porting tool. With this feature included, IP designers can not only port designs to new process nodes, they can also simulate and compare the outcomes of the original and ported designs, using their preferred simulator tool and see if any further adjustments are needed. This reduces the requirement for multiple iterations and saves design porting time.

A new feature included within the AMALIA 24.1 release is a report that provides a summary of the in-depth results from AMALIA’s Technology Analyzer findings.

“This latest enhancement to our software suite uses AI to provide a concise summary of key findings and recommendations taken from the standard report which, due to its comprehensive nature, can be hundreds of pages long. This drastically reduces the subsequent analysis time by providing the most relevant and critical information in a format that is quick and easy for senior designers and key decision makers to understand and make informed decisions,” Syed Ahmad explains.

The release of AMALIA 24.1 reflects Thalia’s dedication to supporting the semiconductor industry’s evolving needs, by not only maintaining up-to-date technology support but also by innovating and enhancing the user experience through new features that simplify complex processes.

For more information on how AMALIA 24.1 can facilitate your IP migration and optimization projects, saving both time and budget, click here.

Thalia’s AMALIA qualified on 12nm FinFET technology

by Sou Bennani-McCordPress Release

Thalia has announced the qualification of its AMALIA platform for 12nm FinFET technology, marking a significant step forward in analog, mixed-signal and RF IP design migration. This qualification enables customers to capitalize on the latest in advanced process technology and accelerate time to market for new products without compromising on cost and resource efficiency.  

“FinFET technology delivers substantial performance benefits and enables more efficient scaling in semiconductor devices. This is crucial given the shift towards increasingly smaller technology nodes and transistors,” says Sou Bennani-McCord, Global VP of Sales at Thalia. 

“Leveraging FinFETs, our customers are engineering devices that are not only smaller and more efficient, but also significantly more powerful, all while ensuring compatibility with a variety of technology nodes. This versatility is key for applications spanning from automotive to IoT, AI and ML, and more, positioning our customers at the cutting edge of electronic design innovation.” 

AMALIA offers a smooth and reliable IP migration cycle helping semincondor companies maintain competitiveness by adopting state-of-the-art process technologies, like 12 FinFET. It also enables them to speed up their product development cycles, while staying on budget and remaining efficient operationally. 

By combining an automated IP migration flow with design expertise, the AMALIA software suite simplifies the transition to newer technologies giving customers the flexibility to broaden their product portfolio and extend their market reach in the most efficient way. 

The AMALIA platform has a proven track record, with validation across more than 50 IPs in domains ranging from RF and Baseband to PMIC and PLL/ADC, many of which are already in commercial use. The addition of 12nm FinFET technology into AMALIA’s capabilities reinforces Thalia’s dedication to innovation and its commitment to ensuring its customers remain at the forefront of technology. 

Click here for more information about Thalia and the AMALIA platform.

Thalia’s AMALIA (23.4a) qualified on Siemens AFS for increased analog design migration flexibility

by Syed AhmadPress Release

Thalia, a leader in analog design migration, today announced the release of AMALIA 23.4a. This latest version of the software suite significantly broadens its capabilities by integrating full support for Siemens AFS Simulator in its Technology Analyzer (TA), Circuit Porting (CP), and Design Enabler (DE) tools.  

“AMALIA was built based around Cadence workflows”, explains Syed Ahmad, VP of Product Development at Thalia. “The added support for Siemens AFS is the first step in a transition to supporting multiple EDA tools to fit all customer design flows and underlines Thalia’s commitment to offering designers unmatched flexibility and efficiency.”  

AMALIA‘s central offer remains the same: dramatically reduce the time, complexity, and costs traditionally associated with migrating and optimizing existing IPs for new technologies and applications. This allows customers to focus simultaneously on both new product development and efficient migration of existing IPs to expand existing product ranges and target new markets and applications. 

Key enhancements in the AMALIA 23.4a release include: 

AMALIA Technology Analyzer (TA): 

  • Integrated device & parameter recognition modules: Modular functionality for more accurate device and parameter recognition. Enhanced auto testcase generation minimizes manual interventions, streamlining the workflow and saving time. 

 AMALIA Circuit Porting (CP): 

  • Simulation comparison: Compare the simulation results of both original and ported designs. Users can determine if the ported design needs further adjustments or if it can be used as it is, ultimately reducing the need for multiple iterations. 
  • Database checker: Before and after the porting process, customers can now examine the database for design completeness and uncover any hidden errors. This step ensures that designers work with a clean database, avoiding unnecessary iterations, thereby saving time and providing a foundation for improved results and error-free porting. 

AMALIA Design Enabler (DE): 

  • Multiple testbenches: Customers can now center several testbenches simultaneously, all using the same design schematic. This facilitates improved optimization leveraging bespoke AI technology.  
  • Regions of Operation: This ensures that the transistor devices operate in the correct region, speeding up the design centering process. 

In addition to these new features, AMALIA 23.4a introduces different licensing levels, offering a flexible approach to cater to individual business requirements.  

While customers can choose to use individual software tools or the entire suite, AMALIA‘s diverse business model now encompasses both licensing and commercial SaaS-based solutions. For those preferring an in-house approach, Thalia can set up and facilitate the use of the AMALIA software directly on the customer’s servers, ensuring IP security within a controlled environment. 

Looking ahead, Thalia has confirmed that the next AMALIA release is scheduled for January 2024. This emphasizes Thalia’s commitment to ongoing improvements in analog and mixed-signal IP reuse and design.

Click here for more information about Thalia and the AMALIA platform.