Category: News & Events

IP reuse and artificial intelligence were two of the major topics at this year’s IP SoC Santa Clara Conference and Exhibition, which took place earlier this month. Thalia’s CTO, Sowmyan Rajagopalan, speaking at the conference, outlined an innovative Reuse Platform as a Service (RePaaS) strategy, allowing analog IP providers to expand their product range and tailor offerings exactly to customer needs; while elsewhere speakers addressed the need for the analog design community to better serve emerging markets such as autonomous driving.

IP reuse and proliferation was a major topic of the conference. IP democratization is no longer a “nice-to-have”, but a “must”, to support the growth of complex SoC design and the new generation of protocols such as 5G, and emerging products such as LIDAR for autonomous vehicles and infrastructure for portable medical imaging. The event addressed the emergence of new business models and contracting processes, and the proliferation of IP, mostly for analog and mixed-signal block designs.

One of the many interesting presentations came from Seamless Microsystems, and was entitled “ADCs for Autonomous Driving”.

The company presented a number of advanced technologies for ADC IP based on a switched-mode signal processing approach.

The first generation of products to benefit will address the medical imaging and 4G/WiFi markets. The company already has silicon-proven devices in TSMC’s 28nm HPM process. The next generation of products is geared for the high bandwidth requirements needed for LIDAR, 5G wireless, and G.fast communication systems. They will potentially need to port it to various technologies and process nodes.

In tune with this theme of IP proliferation and reuse, Thalia’s CTO, Sowmyan Rajagopalan, outlined how our AMALIA design automation technology, combined with in-house analog design expertise and unique design flow methodology, offers an easy path to deploy and quickly diversify a wide portfolio of analog, mixed-signal and RF IP.

Sowmyan demonstrated an innovative approach to make Analog IP Reuse a reality based on robust and silicon validated design completions with customers.

Thanks to our reuse platform-as-a-service (RePaaS), Thalia is able to offer to the market a reliable and trusted solution that can also extend the generation of product variants and design enablement, allowing customers a fast deployment of numerous products.

You can download Sowmyan’s presentation here.

Other presentations at IP SoC 2019 made it clear that the move towards semiconductors for artificial intelligence and machine learning is now in full swing. Many companies are strongly considering both technologies. Indeed, the explosion in AI is inaugurating a new era for chip devices that will offer new scope but also new challenges: exemplified by Synopsys’s presentation entitled “Overcoming AI SoC Design Challenges with IP”. With AI, the number of new opportunities will be huge and more than 50 startups are now working to develop new AI chips with VC investments. Stay tuned!

The IP SoC 19 Santa Clara Conference & Exhibition is one of a series of events that bring together some of the leading minds in semiconductor IP, related applications and ecosystems, in Western Coast.

Delegates from different companies, large players, SMEs and startups, meet for one day of presentations, discussions and panels. The 2019 edition, which took place during the first week of April, was attended by around 150 visitors and 20 exhibitors.

As 2019 moves into full swing, I find myself looking forward to what we hope to achieve at Thalia in the coming year, and at the same time reflecting with great pride on how far we progressed in 2018.

We started 2018 on a high, having been able to publicly disclose that Catena is using our unique combination of analog design automation and expertise to make a fundamental shift in its approach to the creation and delivery of analog IP.

A few short months later we were able to confirm the first tape-outs of projects under that agreement – including migration of a WiFi RF solution to Global Foundries’ 28nm process; migration of Bluetooth IP between TSMC and Global Foundries processes; and a second low power Bluetooth IP migration between 28nm and 40nm nodes.

According to Kave Kianush, Catena Vice President and Chief Technology Officer, these projects provided “strong validation of Catena’s new, more agile approach to analog IP creation and reuse”. Kave also praised Thalia as “instrumental in delivering these projects on-time, to-budget and, just as importantly, to-specification”.

After a successful rebrand and website relaunch in the spring, we were also able to get our message heard at a number of industry events, including Cadence CDNLive EMEA; TSMC Technology Symposium events in Amsterdam, Netherlands and Herzliya, Israel; and IP-SoC 2018 in Grenoble, France.

Demonstrating analog migration

At CDNLive it was particularly gratifying to be able to demonstrate our AMALIA analog migration flow for the first time at a public event. My presentation at the conference – “Analog IP Reuse & Process Migration: Challenges & an Innovative Methodology to Address Them” – illustrated the changes we see in analog design. I believe that human expertise is indispensible, but that some aspects of the analog flow can be sped up and improved using design automation. Migration is a great example – traditionally, a process change has meant a redesign: but as our work with Catena illustrates, there’s plenty we can do in terms of tools and methodologies that support the designer and make the process more efficient.

Analog design reuse – a new approach

TSMC’s Symposium always offers a great opportunity to gauge the pulse of the industry, and this year’s events were no exception. Our CEO Rodger Sykes and Sales Director Jean-Francois Lambert were able to introduce many potential customers to our analog design offering – not only in schematic porting and process migration, but also explaining our ability to facilitate the generation of design variants, and increase performance of existing analog IPs.

Focusing on schematic porting

At the IP-SoC event we were more focused on schematic porting, and once again my presentation was greeted with a lot of interest. We’ve already published a case study on this aspect of the flow, and I was able to provide some detailed facts and figures on the RoI of our new approach to analog design.

Moving into 2019

I’m expecting 2019 to be another exciting year – we’ll have more news on our products and technology developments, expansion in the team, and more significant corporate announcements expected soon.

Thanks for your support and interest in Thalia in 2018, and here’s to a successful coming year!

The IP SoC Grenoble Conference & Exhibition is a yearly get-together of some of the leading minds in semiconductor IP, related applications and ecosystems, in Europe. Executives from different companies, large players, SMEs and startups, meet for two days of presentations, discussions and panels. The 2018 edition, which took place during the first week of December, was attended by around 150 visitors and 20 exhibitors.

One of the most interesting presentations came from TSMC, and was entitled “Designing with TSMC Open Innovation Platform (OIP) Ecosystem”.

The company presented a number of advanced technology highlights including 22ULP/ULL. This new technology is actually a shrink of the 28nm technology. Overall the technology offers 10% die size shrink, 10% performance improvement, 20% power reduction and RF enhancement over 28HPC+. It has been adopted by consumer, 5G mmWave and mainstream RF applications.

Both 22ULP and 22ULL can serve numerous market segments, including: application processor and baseband SoCs, STB, DTV, mmWave RF, mmWave car radar, WLAN (WiFi, Bluetooth LE, etc), GPS, GNSS, flash controller, MCU, audio and IoT.

Many companies are currently launching new SoC designs using TSMC 22nm process nodes, and IP assets need to be consolidated and redesigned to these new processes and nodes. It was therefore timely that Thalia’s presentation at the conference focused on how such process migration can be made easier and more efficient.

Our CTO, Sowmyan Rajagopalan, outlined how our AMALIA design automation technology, combined with in-house analog design expertise and design methodology, offers a simple way to deploy a large portfolio of analog, mixed-signal and RF IP in a very quick turn-around-time.

Sowmyan showed some specific examples of analog migration projects, based on our real-world experience with customers. These included both individual blocks such as PLLs, and complete analog IPs, such as WiFi or Bluetooth front end designs.

It’s worth also noting that the very same approach can also help with generation of product variants and design enablement, allowing customers not only to gain the benefits of new processes and nodes, but also to diversify their product range quickly and easily.

Thalia’s CTO Sowmyan Rajagopalan looks at the RF/analog and mixed signal challenges presented by the proliferation and diversification of Bluetooth technology

This year’s Bluetooth World marked the technology’s 20th anniversary. Although it’s now a mature wireless communications technology, the pace of its development shows no signs of slowing, with Bluetooth 5 and mesh networking high on the agenda at the event. Applications also continue to diversify: in the words of the Bluetooth SIG, “Bluetooth is now poised as an industrial-grade connectivity solution that will be the wireless constant in the IoT for decades to come”.

A year after its launch, Bluetooth mesh is gaining considerable traction; we have Bluetooth 4.0, which itself includes a standard high-speed mode, a low-energy mode with limited data rate, and a single-mode Bluetooth LE standard designed to keep power consumption to a minimum.

One of the other main messages from the SIG in its 20th Anniversary videos was simple: Bluetooth is good because “it just works”. It’s an attractive selling point for end users. But behind the scenes, the diversification and proliferation within the standard poses a challenge for designers, particularly in the analog, RF and mixed signal domain. And the performance metrics that engineers understand – transmission range, data rates, broadcast/multicast capacity – are not getting any easier to satisfy.

It’s becoming increasingly difficult for Bluetooth IP providers to address all of these requirements with a full range of solutions – and even more of a challenge to ensure that customers have the flexibility they need to choose the right process technology and foundry partner.

Like any challenge, this also presents opportunities. I agree with the Bluetooth SIG that we will continue to see rapid growth in the technology’s deployment. But for analog IP providers, grasping that opportunity means changing they way they think.

We need to take a more agile approach to analog IP creation and reuse; to deliver ‘IP on demand’ in this diversified Bluetooth world. Engineering teams within IP providers need routes by which they can create product variants, optimize performance, and rapidly retarget existing IPs to new processes and geometries.

Automation is part of the story here, but is by no means a ‘silver bullet’. It needs to be combined with the expertise of experienced analog designers.

At Thalia we advocate a system-level approach to the problem, encompassing both the specific behaviour of individual IP blocks and the overall performance of the complete system. Every IP we work on is verified and optimized for specification performance in the target process. We can retarget, fine-tune or produce variants of a complete Bluetooth front end solution in weeks. For example, we recently announced successful tape-out of a sub-40nm retargeting project with our customer Catena.

As Bluetooth World showed, the world of wireless communication is changing. Analog design needs to change along with it.

You can find out more about our solutions for Bluetooth IP providers here