Category: Blog

Technology agnostic analog circuit and IP migration

by Sowmyan RajagopalanBlog

Every time you move your designs onto a new process or technology node, the analog circuits and IP need to be implemented. The fact is, managing the migration of these isn’t always the easiest since, as yet, there is no high-level description – as exists in the digital domain.

There are smart ways to reuse part of the layout and schematics for simple designs. However, for complex SoCs to take full benefit of the integration nodes these simple migrations are not recommended.

If you move foundries, the challenges become even more complex as most of them have their own philosophy on creating the PDKs and coping with the latest challenges of sub-nano technology nodes.

For effective decision-making surrounding a circuit design (or redesign), engineering and business planning needs to be able to easily compare the overall business-case, from the feasibility of the design down to the foundry wafer prices and availability of fab capacity and ultimately, to the price of the final device at specific quantities.

It was this set of challenges, and the need for simplifying designers’ lives, that led us to develop the Amalia Technology Analyzer. In the hands of our customers’ design engineers, this powerful tool gives them the option to compare foundry technologies in the shortest time, and informs their strategic planning: enabling them to decide on the right design options and the optimum commercial fit.

Using Technology Analyzer, design teams select the source and target technologies to estimate the best fit, as shown in Figure 1.

Fig 1

Technology Analyzer enables simulations down to device level, using SmartSpice or Spectre, giving the design teams the necessary insights to compare and qualify practically all existing foundry and technology nodes that might fit that specific design. It also gives the possibility to compare the overall costs of productization across different fabs.

And that last point is fundamental when, as is the case today, fab capacity is under extreme pressure and is booked up by a small number of Tier 1 tech companies. The ability to make fast decisions can be crucial to finalize an implementation and to get your product market quickly – hopefully before it’s even too late to maintain your competitive advantage.

If you are under these pressures and this sounds all-too familiar, get in touch with us here and see how a Thalia AMALIA solution can help your business.

How repeat IP reuse delivers significant savings

by Rodger SykesBlog

When IP reuse is implemented quickly and easily, small cost savings can turn into good profit margins. Thalia Chair Rodger Sykes explains how when you maximize the number of repeat reuses, you also maximize the potential for efficiencies and cost savings.

The development of a new chip involves significant upfront costs and investment. The higher the complexity, the greater those costs and the more difficult it can be to make profit. Product marketing teams look to product diversification, differentiation or simply expanding or updating their range of products to maximize the potential for profitable reuse – all which potentially can, or must, be replicated across multiple process technologies.

If we’re talking about the economics of our business model, let’s state clearly upfront: whichever way you look at the economics, analog IP reuse is a cost-effective strategy in process migration. Using Thalia’s AMALIA IP Reuse platform, our customers are able to reduce the time and the costs of their IP reuse and this can save up to 40% which enables them to not only cover all of the initial design and the reuse, but to make a good profit.

While developers do appreciate how IP reuse can increase profitability and help them to recover some of the costs – they are often still often left wondering why they have only covered development costs and can barely break-even.

Quantifying the level of cost saving is not always straightforward: for a start the savings are not only $ savings. Competitive advantages in terms of time-to-market, and design time saved, or simply the reduction in component or IP costs are all significant factors.

Still sounds straightforward, doesn’t it? Saving money or time, amounts to the same thing, right? And it’s all positive. Well, yes – and no.

Savings are all positive, but there are other approaches to design that can also save money and/or time. Developing a clearer understanding of the potential benefits of IP reuse means maximizing the potential savings.

It’s when IP reuse is implemented quickly and easily that small cost savings turn into profit margins. When you also maximize the number of repeat reuses you maximize the potential for efficiencies and cost savings.

Looking at the mix of our customers we can examine where the greatest gains are consistently made. Firstly, it’s the speed of implementing IP Reuse using Thalia’s AMALIA platform that makes a significant difference to those timescales. Secondly, the economic arguments supporting IP reuse are fundamentally economies of scale – and the numbers get really interesting when a continued reuse strategy is at the heart of customers’ design strategy.

Just isolating cost savings, we can see that casual, ad hoc reuse might deliver savings of the order of 2-3X. But, when design teams plan intelligent repeat reuse of IP blocks, across multiple designs, ported to multiple processes – and then go a stage further and apply this across the entire product portfolio – savings ramp up quickly. Design costs decrease exponentially with each instance, or each generation of reuse. Beyond a sixth reuse, customers tell us costs become insignificant – the savings and benefits are significant.

Beyond the financials, the design team’s familiarity with specific, trusted IP can count for significant economies in terms of efficiencies: saving design time, eliminating headaches and enabling the team to reach the optimum final design, ported to new processes in the shortest possible timescales.

If design reuse applies automated intelligent tools, employing self-learning AI tools, such as the Thalia’s AMALIA Design Enabler, then this further enhances time and cost savings as the tools will benefit from existing acquired intelligence, finding its way to the optimum design solution in the least possible time.

Circuit Porting shouldn’t be a shot in the dark

by Sowmyan RajagopalanBlog

To stay competitive, migration is essential: supporting smaller (or larger!) process nodes, alternative fabs, or diversify designs without starting from scratch. Non-recurring engineering (NRE) costs can undermine product marketing strategies: making migration or diversification prohibitively expensive and eroding your competitive advantages in the market.

Done correctly, it is possible to benefit from savings of 50 percent in both development times and costs, by intelligently employing a strategy of IP reuse to support opportunities for extending your existing products to newer processes or product variants.

However, migrating large analog or mixed-signal circuits can itself seem time consuming and can expose re-designs to problems that can be costly to resolve:

  • Mapping the circuits is time consuming and it’s easy to make mistakes
  • You need to account for scaling when porting to different process nodes
  • You need to follow all target device parameter restrictions and create a solution to keep device parameters consistent with source designs

Without insights into where there may be problems or where there are room for improvements, designers have no insight into tolerance limits. They won’t find out about these limits until they run into them – and that’s usually too late.

All of this leaves a re-design open to potential issues which could affect design times, impact performance, as well as undermine the potential profitability of the entire process migration.

A circuit porting tool such as AMALIA OA Circuit Porting (for OpenAccess database) from Thalia, provides a familiar Cadence Virtuoso environment to quickly and easily port circuit designs.

Key steps in circuit porting using AMALIA Circuit Porting OA:

  • Mapping file (Device Mapping file generator)
  • Select your designs (easy-to-use GUI)
  • Port automatically
  • Automatically solve issues with target parameter restrictions
  • Compare existing and ported designs, errors are flagged and highlighted for easy identification
  • Verify the resulting design on the new process

 To allow customer engineering teams to focus on developing new innovative solutions, it’s important that the IP reuse tasks such as circuit porting are supported by a strong team – this is as important as the porting tool itself. The Thalia team behind OA Circuit Porting includes experienced tool developers, mathematician, and hands-on system developers – offering customers a complete understanding of how best to port your design.

Main UI of OA Circuit porting:

OA circuit porting toolbar:

Chiplets and IP reuse made easy: Smaller node ASICs are not always the best way forward

by Sowmyan RajagopalanBlog

Chiplets are a relatively new trend in helping designers of large complex system design to enable a cost-effectively modular approach to designing with costly SoCs. I say relatively because proposals started back in 2016 when DARPA used it as part of its CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program.

To quote DARPA, “The monolithic nature of state-of-the-art SoCs is not always acceptable for Department of Defense (DoD) or other low-volume applications due to factors such as high initial prototype costs and requirements for alternative material sets.”

If you look at the economics of SoCs it’s easy to understand why chiplets are of increasing interest to a wide range of system designers – not just the likes of DARPA: moving from a 45 nm process to a 16 nm process more than doubles the cost/mm². Migrate again to a 7 nm process and costs / mm² double again – that’s 4x the cost per yielded mm².

Chiplets do sacrifice some space (around 10 percent) for the ‘chiplet architecture’ – i.e. the chip interconnects, but the overall benefits of chiplets on total system costs is substantial.

The fundamental benefits of a chiplet approach are: low cost and easy way to repurpose the design and enable variants, with some die-to-die interconnect, a range of third party chips can be combined into a package. One of the most important contributing factors enabling the chiplet approach to system level design is today’s advanced packaging technologies.

Many of the benefits and how chiplet design works may sound rather familiar because it’s what Thalia Design and others in the IP Reuse industry have been enabling for decades. In fact, we see huge potential in chiplets and, done correctly, a strategy of reusable chiplets will present enormous time and cost savings. Time to market, ease of design / migration to new processes, familiarity with the design…all of the benefits Thalia’s AMALIA (TM) IP Reuse platform enables.

When approaching the chiplet design, you can create a portfolio of IP for dedicated functions, even before committing the design to silicon. This makes your chiplet design both technology-agnostic and fab-agnostic.

Thalia’s AMALIA Circuit and IP reuse platform gives you that flexibility. Thalia methodology ports your existing chiplets to new technology nodes or fabs in the shortest possible time.

Commercial considerations can be taken into account during the implementation. For example, if the final solution needs to use a specific foundry, for strategical reasons, the chiplets can be quickly and easily ported to that specific foundry and even technology node.

That raises the levels of flexibility in complex system-level implementations and also gives customers the maximum flexibility in defining their system-in-package solution.

The AMALIA platform only needs the chiplet source technology database and PDK, plus the target technology PDK. AMALIA can also help to create a complete chiplet portfolio. Thalia IP reuse suite of products can handle the complete design, reuse or migration of the chiplet in practically every fab or technology node.

Thalia’s partner network also provides the productization of chiplets in specific foundries, down to 7nm technology nodes.

If you are planning your own chiplet strategy, get in touch with us to find out how AMALIA platform can help to further simplify the IP reuse.

AI: when is it ‘really’ intelligent?

by Sowmyan RajagopalanBlog

Artificial Intelligence is quite obviously a buzzword which attracts significant marketing hype – that has been the case for a decade at least. There are countless number of high-profile examples where AI is used to simply describe an automated (usually software-enabled) routine. Good examples of this can be seen in Facebook’s use of AI: filters that simply track and flag keywords, or images, that break a set of human-defined rules. The fact of the large number of false positives they ‘capture’ demonstrates that, while these programs may be artificial, they’re not always intelligent as we humans would define it. They are, more often than not, just forms of computational automation.

Don’t get me wrong, computational automation can be beneficial, it can speed things up and save significant time, hence money. But it does not add skills, nor does it bring added, intelligent value to a design team – which is what we’re trying to do for our customers. Given the wide and potentially misleading use of the term, there is no doubt that when we chose to use AI to refer to the capabilities of our AMALIA Design Enabler we really had to pause and check we were being honest with ourselves, and with our customers.

AMALIA Design Enabler passes the acid test. We threw problems at the system, asking it to find solutions to problems – looking for answers we didn’t know existed. In the video, you can see a perfect example of its application and the benefits of a truly-AI solution for supporting design problems: helping the designer to compare and assess alternative components to resolve a technical issue with the system. In this case, during a process migration, a very low current voltage regulator was taking far too long to achieve a zero temperature coefficient state… to compare the options and find a solution just in the small circuit in question could have taken the design team several weeks.

By entering the requirements into AMALIA Design Enabler, along with the options available, the Design Enabler AI algorithm was able to find its own way to the answer in relatively few steps and a very short amount of time: reaching the answer in just 40 steps, in spite of there being thousands of potential variables.

The reason we’re confident in calling the Design Enabler true-AI, is exactly that: the system is learning as it goes, changing direction based on initial findings and zeroing-in on the correct solution: it is not simply observing, calculating, and running every possible scenario before ‘happening’ upon the correct answer by brute force and computational power.

So, AI is dead. Long live AI! We believe that true-AI does have a place in design automation. Selecting the appropriate components and enabling appropriate IP reuse in process migration can be a complex, time-consuming task – but when it’s done well, it significantly improves design profitability and system performance.

Long tail supply chain ramifications

by Sowmyan RajagopalanBlog

supplychainAs the world recovers from the global pandemic and vaccination programmes gain pace, the tone of news is, on the whole, optimistic. As the focus moves to economic recovery and a return to something resembling normality, many sectors are breathing a metaphorical sigh of relief.

Elsewhere are worrying signs that the knock-on effects of the pandemic are only now beginning to surface. Factories that shut down and are now ramping back up to capacity are finding they are coming back online only to face supply chain issues as capacity in component supplier factories has shifted to other priorities.

The automotive sector is one of many affected. Modern cars have an abundance of technology – recent reports suggest 150 million lines of code and up to 100 different processors. As the pandemic hit, automotive manufacturing slowed as demand stalled, and only now that other sectors are opening up are demand forecasts suggesting that the time to ramp up production has arrived. But the supply chains that are relied upon for the sensors, circuits and processors have been diverted to service sectors that didn’t stall, and in fact thrived, through the pandemic.

Sectors including wireless, IoT, personal comms and video streaming have burgeoned through the pandemic. Zoom’s revenues had quadrupled by September 2020, and Microsoft reported a 50% increase in daily active users and neither are expecting this increase in demand to drop off. So when automotive demand dropped, fabs switched their attention – and capacity – to service sectors that were thriving. It’s good business.

But those same fabs aren’t going to switch back at the drop of a hat when the car industry calls – contracts are signed, processes in flow and capacity simply isn’t there. Fabs slowed down the expansion of their wafer capacities as demand was lower. It takes time – from 20 weeks up to a year or two to bring a wafer fab online, so simply increasing capacity isn’t an option either. Instead, the fabs are in a position of strength, with their services in high demand, so the long-term picture, for them at least, is strong, but for sectors that experienced a drop in demand and revenues and were anticipating a resurgence, it seems the true impact of the pandemic is only now starting to take effect.

It’s rumoured that TSMC’s 5nm capacity is all taken up by Apple, and Samsung are in a similar thriving position, with reports that their legal teams are all engaged in managing NDAs and contract negotiations and have no capacity to discuss new engagements with prospects.

So while some win, others lose out. In the long run, things will inevitably find some type of equilibrium, but in the short term is there a learning to be taken? Could IP reuse shortcut at least some of the delay?

Perhaps. But supply chain resilience is a huge and escalating issue. There are other socio-economic issues in the mix too with tensions around political topics in the far east, anxieties are certainly high. There has never been a more important time to ensure your supply chain is robust, resilient and reliable.

This is an issue occupying many in Europe and the US. With the issue now top-of-the pile for leading politicians globally – not least in the White House – one positive outcome is likely to be the development of new manufacturing plants closer to home.

Interesting to note that since I posted this blog the subject has gone mainstream – for example, in a recent news piece from the BBC, the Harvard Business Review and the Guardian.

 

Fabs, foundries and fame

by Sowmyan RajagopalanBlog

While our USP is in circuit and IP reuse, our ongoing engagement in technology transitions is almost as important. We’re working with all of the major names in the semiconductor industry to enable a cost-effective and high-quality transfer process.

There are a number of transition scenarios. For fabless companies and design houses, Thalia assists the development teams, helping them in the reuse of analog and mixed signal circuits and IPs with the AMALIA platform. The source and target foundry can be selected by the customer and qualified using Thalia’s Technology Analyzer, but Thalia also has the ability and expertise to advise on both node and foundry selection. Next, our experienced design team and proprietary Design Enabler is used to center the target design in the fastest and most efficient way.

On the other hand, for companies who prefer to use their own fabs and internal design teams, we offer our circuit and IP reuse platform adapted to their specific EDA environment (Cadence, Silvaco, Siemens EDA, Synopsys).

Quite often, IC design groups don’t have the in-house capabilities of a specialist company like Thalia to effectively adapt their EDA tools and tune their framework to specialised needs.

Selection of logos of fab companies

Figure 1: Targeted semiconductor fabs and foundries

In recent years our circuit and IP reuse platform has grown in popularity, largely because of the demonstrable benefits it delivers. These include:

  • an efficient upfront qualification of the target process technology
  • reduced design and redesign cycle time
  • the swift generation of a portfolio of IPs.

We can also deliver improved performance, power and area of reused circuits and IPs.

Importantly too, we adapt the design reuse process to our customers’ needs. Thalia can take the full ownership of all aspects of migration or reuse including schematic architecture and layout and any re-centring or revisions that are needed.

Our business is to transition designs and our experienced designers, advanced methodologies and our automated AI based platform mean we are much more efficient and effective in this than many design houses. If we save up to 50 percent of the time that might otherwise be taken up in such a redesign, money is not only saved on worktime, redesign and people, but also on tools. The potential savings for our customers is in the order of tens of thousands of dollars – and we’re enjoying a lot of success.

Diagram showing time saving possibilities

Figure 2: Examples of time savings delivered using AMALIA platform

Completing engagements faster and at less cost brings two significant additional benefits to our clients:

  • Completing migrations faster means they are the first to market, gaining a competitive edge that is hard to overcome, and
  • With lower development costs, return on investment is achieved much sooner. If costs are halved (for example) then the number of licenses of a given product that need to be sold to recoup development costs are vastly reduced.

A growing fame in a growing market and working with the worldwide foundry leader for many years, delivering fantastic results time and time again, we’re justifiably proud of what we are achieving.

Isn’t it time you found out what we could do for you?

How open is OpenRAN?

by Sowmyan RajagopalanBlog

Why is OpenRAN important and what is its likely impact on the silicon market?

While these are questions I often hear, it’s difficult to give a precise answer as there is still an amount of uncertainty over the details of OpenRAN and depending how the evolution progresses, the response will be tailored accordingly.

A truly open OpenRAN would indeed have extraordinary promise. However, a vendor-neutral hardware and software-defined technology based on open interfaces and community-developed standards is not a given. Certainly, openness on the hardware side of the equation is far from guaranteed.

That would not necessarily be an end to the matter. If software – and the interface software in particular – became totally open, that really would be a game-changer. Generic software would bring down costs significantly. The business model for 5G would be transformed, and 5G IoT in particular would undoubtedly benefit.

Think of the average household. How many devices were networked five or six years ago? Four or five perhaps? By contrast, today a home with 25 or more objects wirelessly linked or enabled – cameras, radios, virtual assistants, hi-fis, tablets, laptops – wouldn’t be a surprise.

Many of these rely on Wi-Fi. But a genuinely low-cost 5G enabled by truly open RAN protocols could become a credible alternative – and not only in the home. 5G support for IoT, made more cost-effective via OpenRAN – could turn some fairly fanciful scenarios into reasonable business models. It could mean, for example, that turning your own car into a hub would be a good investment.

And ubiquitous 5G – again enabled by non-proprietary software – could have a transforming effect on phone manufacture – and cost.

But will OpenRAN really be open? We won’t know for sure when the first iteration of 5G rolls out; it’s too early for OpenRAN to influence it. Much of the protocol and standards work is still being done.

But when 5G 2.0 appears, the usefulness of a truly open RAN will be clear – if that is actually what OpenRAN delivers. Hardware supply is still dominated by a few major names, and it’s hard to see that changing. There is, however, more optimism on the software front. We shall see.

As for semiconductors, new protocols and enhanced compute powers would be part of a number of changes that would almost certainly make many new – and appealing – demands on the semiconductor space – or they could, if OpenRAN’s promoters really mean what they say.

In reality, the concept of OpenRAN will be an evolving process and as things become more clear in subsequent iterations / generations of the protocol, it will become clear which players are active on specific architectures and what type of truly open access can be brought about in this space.

Solving the problem of growing ASIC respins

by Rodger SykesBlog

Semiengineering.com recently reported on an industry survey showing an increase in respins due to analog circuitry failing or falling out of operable range.

The reasons behind this trend are complex, but the article suggests it comes down to analog tuning – the process of tweaking a design to maximise performance while staying within the operational parameters of the overall circuit. The article also explains that the chief scientist at Mentor, a Siemens Business, analysed the results to determine the scale and scope of this trend – whether it was affecting newer designs on the latest technology nodes, or if it was a universal problem.

Figure 1: Flaws contributing to ASIC re-spins. Source: Wilson Research and Mentor, a Siemens Business

It would be easy to assume that the problem was relating to newer nodes and newer processes, but on review, the issues are affecting technology nodes from sub-7nm to 150nm and higher.

Figure 2: Tuning analog circuit flaws by design size. Source: Wilson Research and Mentor, a Siemens Business

So what’s causing the increase in failures?

Put simply, the complexity of new devices. The number of complex devices is growing, and is set to continue with the expansion of the IoT. Automotive components are also massively on the rise, both in number and complexity, thanks to the developments towards self-driving cars. Companies are trying to fit all circuitry on the same substrate or on a single technology node and schematic simulation isn’t able to accurately assess function and full parameters.

Fig 3: Defect rates for automotive ICs and causes of failures. Source: Mentor, a Siemens Business

There will always be issues arising when working with new nodes and there is a learning curve for design teams to fully come to terms with the limitations, issues and particular traits displayed by these new nodes. Implementing this knowledge into toolsets is only achievable once they are fully understood. But if that learning curve therefore involves respins and ‘back to the drawing board’ moments at increasing frequency, then time to market will be affected for new devices. And increasing time to market for a new chip in a competitive industry can be the difference between market success and failure. Second place really is the first loser.

As IP reuse specialists, this is not news to us. We have worked with many clients evolving analog IP from one technology to another or even from one foundry to another. Most engagements are accompanied with the need to improve power consumption, speed, performance or the physical size of the silicon chip, and when these needs are implemented, they have knock on effects to other characteristics, resulting in the silicon not performing to specification.

We know this; it’s what we do. It’s why we developed our technology analyzer to be able to identify differences between base and target technologies and highlight where a circuit will fail. Our Trifecta, including the AMALIA platform, helps to identify the root cause of an issue and allows our design engineers to nudge a design back into specification before migration; mitigating the need for respins for out-of-tolerance circuits.

As experts in reusing analog IP on different process nodes or technologies, we’ve spent years developing processes to ensure IP works as expected and as needed in target technologies. We do this by deploying our Trifecta – advanced development methodologies, the targeted automation of our AMALIA platform and our design expertise. Using this Trifecta approach means we can verify IPs and their behaviour or performance before migration. Part of the AMALIA platform uses our proprietary technology analyzer to rapidly identify parameters in both base and target technologies to identify issues, allowing our expert designers to tweak characteristics and knock the design into specification.

This methodology, used by us across multiple technology nodes and foundries, has the potential to play a significant role in the fast and efficient migrating of analog IP for the ever-increasing number of IoT, mobile and handheld devices. Analog components sit alongside digital and ensuring everything functions as it should is key in getting new products to market ahead of the competition.

Hands-free driving – and the technology behind it

by Sowmyan RajagopalanBlog

Hands-free driving could be legal on UK roads by spring next year, the UK government has said. A consultation on the technology involved is under way. Specifically the UK’s Department for Transport (DfT) has issued a call for evidence into automated lane keeping systems (ALKS).

The technology to do this is still very much developing, although we can certainly expect that it will make significant demands on the semiconductor industry that Thalia serves. But first some background.

This consultation looks at level three (of five) on the way to the ultimate aim of completely automated driving. In stage two the vehicle can control both steering and acceleration / deceleration. The automation isn’t classed as self-driving because a human is still required to sit in the driver’s seat and be prepared to take control of the car at any time.

Level 3 vehicles, however, have what are called environmental detection capabilities and can make informed decisions for themselves, such as accelerating past a slow-moving vehicle. The driver must remain alert and ready to take control if the system is unable to execute the task but, in theory, the driver could do other things such as check email or even watch a movie – until the car prompts him or her to take over again.

But don’t get too excited just yet. The UK government’s call for evidence, at some 46 pages, makes some pretty stern safety demands of what it calls ‘a traffic jam chauffeur technology designed to control the lateral and longitudinal movement of the vehicle for an extended period without further driver command’. These demands include a driver availability recognition system, reasonable thresholds designed to prevent unintentional inputs into the override capabilities, a data storage system for automated driving and numerous compliance requirements involving monitoring and control criteria – to name but a few.

But that isn’t all. The ALKS regulation approved in June 2020 by the United Nations Economic Commission is for a system (in its current form) capable of operating at speeds of up to just 37mph. It is therefore designed for situations of heavy, slow-moving traffic on a motorway. Why motorways? Because they go one way and are more controlled and simpler environments than most others. A slow-moving motorway is a good place to try out stage three ALKS.

Elsewhere in Europe, Germany has drafted legislation for level 4 autonomous vehicles. As yet, the legislation remains unpublished, but Germany, as the country of origin for most OEMs relating to the technology behind assisted and self-driving vehicles, could expect to see the reality of self-driving vehicles sooner rather than later. If this is the case, German legislation will likely guide all other nations legislative developments.

Even with the restrictions at levels 3 and 4 of automation, the market seems to be a promising one. According to a report released earlier this year by Acumen Research and Consulting, the global automotive lane keep assist system market is expected to reach a market value of around US$7 billion by 2026 and is anticipated to grow at a CAGR of around 16% in terms of revenue during the report’s forecast period 2019 to 2026.

It will no doubt mean a lot of work supplying a whole new market with tech – and a whole new semiconductor market with relevant IPs. And, of course, this market has a lot of development to do; new requirements, new sensors, new software and new hardware will supersede each other. Within a lot less than ten years, we may see not only level four (vehicles operating in self-driving mode within a limited area) but early level 5 cars: able to go anywhere and do anything that an experienced human driver can do.

As for public acceptance of ALKS, we can certainly assume that even hiccoughs or bad publicity will only slow rather than stop the rollout of this form of automated driving, and that when the first completely autonomous cars arrive – sometime after 2026 in all likelihood – a $7 billion market will just be the start.