Navigating the challenges of manual IP design migrations

In semiconductor design, the migration of IP across different technology nodes is a complex but business critical process. This task, traditionally manual, involves a detailed analysis of source and target technologies, migration of schematics and testbenches, and iterative design adjustments to meet specific performance requirements for the final design layout.

The challenges of manual migration

The manual process is intricate and lengthy, taking weeks to months, depending on the complexity of the circuit and IPs involved. Designers must deeply understand circuit behavior across Process, Voltage, and Temperature (PVT) corners, and engage in extensive simulations and iterations to achieve the desired specifications.

Additionally, the rate at which new technology nodes are introduced is accelerating, with each new node introducing more design rule complexity, leading to higher development costs and greater pressure on engineering resources due to the additional time needed to manage the migration process.

A shortage of skilled engineers further complicates the situation, not only extending design timelines and inflating costs due to the premium on expert talent, but also putting companies at risk of falling behind in the fiercely competitive race to secure fab capacity.

Using automation to maximise resources

However, the landscape is evolving, and there is now a range of tools and software solutions on the market designed to tackle these challenges. A key feature to look out for when considering these tools is the use of automation to reduce manual intervention, streamline the migration of designs to new nodes, and optimize designs to save time and cost thus providing a clear advantage over manual processes.

In response to these challenges, Thalia’s AMALIA platform emerges as a prime example, leveraging AI and ML in its suite of tools for advanced analog design, particularly within the PMIC/RFIC domain.

IP reuse diagram
Engagement time saved using AMALIA platform versus manual migration approach.

How AMALIA addresses the gaps in the traditional IP migration flow

The first tool in the platform is AMALIA‘s Technology Analyzer (TA) which automates the initial and time-consuming process of analyzing electrically comparable devices between the source and target Process Design Kits (PDKs) to significantly shorten the time needed for technology assessment and decision-making that would precede any IP migration.

Next, the AMALIA Circuit Porting (CP) tool builds on this analysis, automating the migration of schematics and testbenches with a high level of accuracy and reliability. This step not only maintains the integrity of the original design but also drastically reduces the time required in manual porting.

If circuit porting alone does not meet all the design constraints, AMALIA Design Enabler (DE) uses AI and machine learning to optimize circuit performance, focusing on critical devices and making targeted adjustments. This results in a design that meets, and often surpasses, the required specifications, significantly reducing iterations and the overall development duration.

Lastly, AMALIA‘s Layout Automation (LA) tool ensures that the intelligence gathered during silicon validation is not lost in translation to the final layout. By automating routine tasks and conducting thorough design rule checks, LA maintains the original placement and floorplan, thus upholding the design’s integrity and facilitating a smoother transition to manufacture-ready designs.

A strategic advantage

The semiconductor industry’s shifting towards automated IP design migration is a response to the increasing complexity and pace of technology development. Thalia’s AMALIA platform delivers a comprehensive solution that bridges the gaps in manual design migration flow and offers a unique combination of speed, efficiency, and precision that significantly reduces design cycle time by up to 40%. In turn, associated costs are reduced and time-to-market for new products is faster, offering a strategic advantage to companies looking to stay competitive in a dynamic market.

To integrate an advanced solution like AMALIA into your design workflow and discuss how Thalia can support your needs, please contact us here.

How open is OpenRAN?

Why is OpenRAN important and what is its likely impact on the silicon market?

While these are questions I often hear, it’s difficult to give a precise answer as there is still an amount of uncertainty over the details of OpenRAN and depending how the evolution progresses, the response will be tailored accordingly.

A truly open OpenRAN would indeed have extraordinary promise. However, a vendor-neutral hardware and software-defined technology based on open interfaces and community-developed standards is not a given. Certainly, openness on the hardware side of the equation is far from guaranteed.

That would not necessarily be an end to the matter. If software – and the interface software in particular – became totally open, that really would be a game-changer. Generic software would bring down costs significantly. The business model for 5G would be transformed, and 5G IoT in particular would undoubtedly benefit.

Think of the average household. How many devices were networked five or six years ago? Four or five perhaps? By contrast, today a home with 25 or more objects wirelessly linked or enabled – cameras, radios, virtual assistants, hi-fis, tablets, laptops – wouldn’t be a surprise.

Many of these rely on Wi-Fi. But a genuinely low-cost 5G enabled by truly open RAN protocols could become a credible alternative – and not only in the home. 5G support for IoT, made more cost-effective via OpenRAN – could turn some fairly fanciful scenarios into reasonable business models. It could mean, for example, that turning your own car into a hub would be a good investment.

And ubiquitous 5G – again enabled by non-proprietary software – could have a transforming effect on phone manufacture – and cost.

But will OpenRAN really be open? We won’t know for sure when the first iteration of 5G rolls out; it’s too early for OpenRAN to influence it. Much of the protocol and standards work is still being done.

But when 5G 2.0 appears, the usefulness of a truly open RAN will be clear – if that is actually what OpenRAN delivers. Hardware supply is still dominated by a few major names, and it’s hard to see that changing. There is, however, more optimism on the software front. We shall see.

As for semiconductors, new protocols and enhanced compute powers would be part of a number of changes that would almost certainly make many new – and appealing – demands on the semiconductor space – or they could, if OpenRAN’s promoters really mean what they say.

In reality, the concept of OpenRAN will be an evolving process and as things become more clear in subsequent iterations / generations of the protocol, it will become clear which players are active on specific architectures and what type of truly open access can be brought about in this space.

Solving the problem of growing ASIC respins recently reported on an industry survey showing an increase in respins due to analog circuitry failing or falling out of operable range.

The reasons behind this trend are complex, but the article suggests it comes down to analog tuning – the process of tweaking a design to maximise performance while staying within the operational parameters of the overall circuit. The article also explains that the chief scientist at Mentor, a Siemens Business, analysed the results to determine the scale and scope of this trend – whether it was affecting newer designs on the latest technology nodes, or if it was a universal problem.

Figure 1: Flaws contributing to ASIC re-spins. Source: Wilson Research and Mentor, a Siemens Business

It would be easy to assume that the problem was relating to newer nodes and newer processes, but on review, the issues are affecting technology nodes from sub-7nm to 150nm and higher.

Figure 2: Tuning analog circuit flaws by design size. Source: Wilson Research and Mentor, a Siemens Business

So what’s causing the increase in failures?

Put simply, the complexity of new devices. The number of complex devices is growing, and is set to continue with the expansion of the IoT. Automotive components are also massively on the rise, both in number and complexity, thanks to the developments towards self-driving cars. Companies are trying to fit all circuitry on the same substrate or on a single technology node and schematic simulation isn’t able to accurately assess function and full parameters.

Fig 3: Defect rates for automotive ICs and causes of failures. Source: Mentor, a Siemens Business

There will always be issues arising when working with new nodes and there is a learning curve for design teams to fully come to terms with the limitations, issues and particular traits displayed by these new nodes. Implementing this knowledge into toolsets is only achievable once they are fully understood. But if that learning curve therefore involves respins and ‘back to the drawing board’ moments at increasing frequency, then time to market will be affected for new devices. And increasing time to market for a new chip in a competitive industry can be the difference between market success and failure. Second place really is the first loser.

As IP reuse specialists, this is not news to us. We have worked with many clients evolving analog IP from one technology to another or even from one foundry to another. Most engagements are accompanied with the need to improve power consumption, speed, performance or the physical size of the silicon chip, and when these needs are implemented, they have knock on effects to other characteristics, resulting in the silicon not performing to specification.

We know this; it’s what we do. It’s why we developed our technology analyzer to be able to identify differences between base and target technologies and highlight where a circuit will fail. Our Trifecta, including the AMALIA platform, helps to identify the root cause of an issue and allows our design engineers to nudge a design back into specification before migration; mitigating the need for respins for out-of-tolerance circuits.

As experts in reusing analog IP on different process nodes or technologies, we’ve spent years developing processes to ensure IP works as expected and as needed in target technologies. We do this by deploying our Trifecta – advanced development methodologies, the targeted automation of our AMALIA platform and our design expertise. Using this Trifecta approach means we can verify IPs and their behaviour or performance before migration. Part of the AMALIA platform uses our proprietary technology analyzer to rapidly identify parameters in both base and target technologies to identify issues, allowing our expert designers to tweak characteristics and knock the design into specification.

This methodology, used by us across multiple technology nodes and foundries, has the potential to play a significant role in the fast and efficient migrating of analog IP for the ever-increasing number of IoT, mobile and handheld devices. Analog components sit alongside digital and ensuring everything functions as it should is key in getting new products to market ahead of the competition.

Hands-free driving – and the technology behind it

Hands-free driving could be legal on UK roads by spring next year, the UK government has said. A consultation on the technology involved is under way. Specifically the UK’s Department for Transport (DfT) has issued a call for evidence into automated lane keeping systems (ALKS).

The technology to do this is still very much developing, although we can certainly expect that it will make significant demands on the semiconductor industry that Thalia serves. But first some background.

This consultation looks at level three (of five) on the way to the ultimate aim of completely automated driving. In stage two the vehicle can control both steering and acceleration / deceleration. The automation isn’t classed as self-driving because a human is still required to sit in the driver’s seat and be prepared to take control of the car at any time.

Level 3 vehicles, however, have what are called environmental detection capabilities and can make informed decisions for themselves, such as accelerating past a slow-moving vehicle. The driver must remain alert and ready to take control if the system is unable to execute the task but, in theory, the driver could do other things such as check email or even watch a movie – until the car prompts him or her to take over again.

But don’t get too excited just yet. The UK government’s call for evidence, at some 46 pages, makes some pretty stern safety demands of what it calls ‘a traffic jam chauffeur technology designed to control the lateral and longitudinal movement of the vehicle for an extended period without further driver command’. These demands include a driver availability recognition system, reasonable thresholds designed to prevent unintentional inputs into the override capabilities, a data storage system for automated driving and numerous compliance requirements involving monitoring and control criteria – to name but a few.

But that isn’t all. The ALKS regulation approved in June 2020 by the United Nations Economic Commission is for a system (in its current form) capable of operating at speeds of up to just 37mph. It is therefore designed for situations of heavy, slow-moving traffic on a motorway. Why motorways? Because they go one way and are more controlled and simpler environments than most others. A slow-moving motorway is a good place to try out stage three ALKS.

Elsewhere in Europe, Germany has drafted legislation for level 4 autonomous vehicles. As yet, the legislation remains unpublished, but Germany, as the country of origin for most OEMs relating to the technology behind assisted and self-driving vehicles, could expect to see the reality of self-driving vehicles sooner rather than later. If this is the case, German legislation will likely guide all other nations legislative developments.

Even with the restrictions at levels 3 and 4 of automation, the market seems to be a promising one. According to a report released earlier this year by Acumen Research and Consulting, the global automotive lane keep assist system market is expected to reach a market value of around US$7 billion by 2026 and is anticipated to grow at a CAGR of around 16% in terms of revenue during the report’s forecast period 2019 to 2026.

It will no doubt mean a lot of work supplying a whole new market with tech – and a whole new semiconductor market with relevant IPs. And, of course, this market has a lot of development to do; new requirements, new sensors, new software and new hardware will supersede each other. Within a lot less than ten years, we may see not only level four (vehicles operating in self-driving mode within a limited area) but early level 5 cars: able to go anywhere and do anything that an experienced human driver can do.

As for public acceptance of ALKS, we can certainly assume that even hiccoughs or bad publicity will only slow rather than stop the rollout of this form of automated driving, and that when the first completely autonomous cars arrive – sometime after 2026 in all likelihood – a $7 billion market will just be the start.