Author: Sowmyan Rajagopalan

This blog is the first in a series of three snapshot articles on the effects of chip shortage on the industry: What impacts is it having? What changes are taking place in the industry, or even in politics, in attempts to guarantee supplies and ring-fence national or regional supplies? And finally, once plans are in place for second-sourcing, or alternative manufacturing, how does that affect design decisions, time-to-market and ultimately, profitability? 

Access to chip supplies – hence to the manufacturing of chips – have become a strategic initiative for companies and nations alike. Lockdowns due to Covid-19 has arguably caused a lot of the ‘tailbacks’ seen in the industry. But while it’s been a catalyst, there are other factors at play and it’s making nation-states and regions start to evaluate the strategic importance of their chip supplies. 

The fact is, in spite of problems with supply chain, or businesses affected in various ways due to Covid-19 lockdowns, demand has not dropped off, and shows no signs of scaling back. Quite the opposite. 

In fact, we’ve seen in recent weeks, the risks of global conflict certainly affect supply and demand and can impact the industry in ways we’d never thought of, with the growing crisis in Ukraine set to affect the supply of palladium and scandium – some of the raw materials used in chip manufacturing:  

But more generally, changes in the geopolitical climate are making chip companies consider and reconsider where they source or where they manufacture. US politics can discourage or stop companies from moving their manufacturing to China for example.  

Global Wafers attempting to invest in Siltronic – but ‘stalling’ for what appears to be political reasons. 

The big wafer fabs are rethinking their own strategies to both keep pace with the chip shortage and to fend off geopolitical risks that may affect their own supplies or access to their customers. Some of this is the Tier 1 chip makers extending their manufacturing, both to other parts of the world, or in the same region to simply increase their capacity. 

But it’s not a quick fix: wafer fabs take a lot of money and typically at least three years to build and become operational. 

In Europe, the $43bn EU chips act is targeting European self-sufficiency to raise its game – aiming for 20 percent of the global market by 2030. The act also is also designed to prioritise Europe’s own needs ‘in times of shortages’. 

The second blog in this series will look at how companies are restructuring and where investment decisions are being driven by the risks of global chip shortages and these geopolitics pressures.

Every time you move your designs onto a new process or technology node, the analog circuits and IP need to be implemented. The fact is, managing the migration of these isn’t always the easiest since, as yet, there is no high-level description – as exists in the digital domain.

There are smart ways to reuse part of the layout and schematics for simple designs. However, for complex SoCs to take full benefit of the integration nodes these simple migrations are not recommended.

If you move foundries, the challenges become even more complex as most of them have their own philosophy on creating the PDKs and coping with the latest challenges of sub-nano technology nodes.

For effective decision-making surrounding a circuit design (or redesign), engineering and business planning needs to be able to easily compare the overall business-case, from the feasibility of the design down to the foundry wafer prices and availability of fab capacity and ultimately, to the price of the final device at specific quantities.

It was this set of challenges, and the need for simplifying designers’ lives, that led us to develop the Amalia Technology Analyzer. In the hands of our customers’ design engineers, this powerful tool gives them the option to compare foundry technologies in the shortest time, and informs their strategic planning: enabling them to decide on the right design options and the optimum commercial fit.

Using Technology Analyzer, design teams select the source and target technologies to estimate the best fit, as shown in Figure 1.

Technology Analyzer enables simulations down to device level, using SmartSpice or Spectre, giving the design teams the necessary insights to compare and qualify practically all existing foundry and technology nodes that might fit that specific design. It also gives the possibility to compare the overall costs of productization across different fabs.

And that last point is fundamental when, as is the case today, fab capacity is under extreme pressure and is booked up by a small number of Tier 1 tech companies. The ability to make fast decisions can be crucial to finalize an implementation and to get your product market quickly – hopefully before it’s even too late to maintain your competitive advantage.

If you are under these pressures and this sounds all-too familiar, get in touch with us here and see how a Thalia AMALIA solution can help your business.

To stay competitive, migration is essential: supporting smaller (or larger!) process nodes, alternative fabs, or diversify designs without starting from scratch. Non-recurring engineering (NRE) costs can undermine product marketing strategies: making migration or diversification prohibitively expensive and eroding your competitive advantages in the market.

Done correctly, it is possible to benefit from savings of 50 percent in both development times and costs, by intelligently employing a strategy of IP reuse to support opportunities for extending your existing products to newer processes or product variants.

However, migrating large analog or mixed-signal circuits can itself seem time consuming and can expose re-designs to problems that can be costly to resolve:

• Mapping the circuits is time consuming and it’s easy to make mistakes
• You need to account for scaling when porting to different process nodes
• You need to follow all target device parameter restrictions and create a solution to keep device parameters consistent with source designs

Without insights into where there may be problems or where there are room for improvements, designers have no insight into tolerance limits. They won’t find out about these limits until they run into them – and that’s usually too late.

All of this leaves a re-design open to potential issues which could affect design times, impact performance, as well as undermine the potential profitability of the entire process migration.

A circuit porting tool such as AMALIA OA Circuit Porting (for OpenAccess database) from Thalia, provides a familiar Cadence Virtuoso environment to quickly and easily port circuit designs.

Key steps in circuit porting using AMALIA Circuit Porting OA:

• Mapping file (Device Mapping file generator)
• Select your designs (easy-to-use GUI)
• Port automatically
• Automatically solve issues with target parameter restrictions
• Compare existing and ported designs, errors are flagged and highlighted for easy identification
• Verify the resulting design on the new process

 To allow customer engineering teams to focus on developing new innovative solutions, it’s important that the IP reuse tasks such as circuit porting are supported by a strong team – this is as important as the porting tool itself. The Thalia team behind OA Circuit Porting includes experienced tool developers, mathematician, and hands-on system developers – offering customers a complete understanding of how best to port your design.

Main UI of OA Circuit porting:

OA circuit porting toolbar:

Chiplets are a relatively new trend in helping designers of large complex system design to enable a cost-effectively modular approach to designing with costly SoCs. I say relatively because proposals started back in 2016 when DARPA used it as part of its CHIPS (Common Heterogeneous Integration and IP Reuse Strategies) program.

To quote DARPA, “The monolithic nature of state-of-the-art SoCs is not always acceptable for Department of Defense (DoD) or other low-volume applications due to factors such as high initial prototype costs and requirements for alternative material sets.”

If you look at the economics of SoCs it’s easy to understand why chiplets are of increasing interest to a wide range of system designers – not just the likes of DARPA: moving from a 45 nm process to a 16 nm process more than doubles the cost/mm². Migrate again to a 7 nm process and costs / mm² double again – that’s 4x the cost per yielded mm².

Chiplets do sacrifice some space (around 10 percent) for the ‘chiplet architecture’ – i.e. the chip interconnects, but the overall benefits of chiplets on total system costs is substantial.

The fundamental benefits of a chiplet approach are: low cost and easy way to repurpose the design and enable variants, with some die-to-die interconnect, a range of third party chips can be combined into a package. One of the most important contributing factors enabling the chiplet approach to system level design is today’s advanced packaging technologies.

Many of the benefits and how chiplet design works may sound rather familiar because it’s what Thalia Design and others in the IP Reuse industry have been enabling for decades. In fact, we see huge potential in chiplets and, done correctly, a strategy of reusable chiplets will present enormous time and cost savings. Time to market, ease of design / migration to new processes, familiarity with the design…all of the benefits Thalia’s AMALIA (TM) IP Reuse platform enables.

When approaching the chiplet design, you can create a portfolio of IP for dedicated functions, even before committing the design to silicon. This makes your chiplet design both technology-agnostic and fab-agnostic.

Thalia’s AMALIA Circuit and IP reuse platform gives you that flexibility. Thalia methodology ports your existing chiplets to new technology nodes or fabs in the shortest possible time.

Commercial considerations can be taken into account during the implementation. For example, if the final solution needs to use a specific foundry, for strategical reasons, the chiplets can be quickly and easily ported to that specific foundry and even technology node.

That raises the levels of flexibility in complex system-level implementations and also gives customers the maximum flexibility in defining their system-in-package solution.

The AMALIA platform only needs the chiplet source technology database and PDK, plus the target technology PDK. AMALIA can also help to create a complete chiplet portfolio. Thalia IP reuse suite of products can handle the complete design, reuse or migration of the chiplet in practically every fab or technology node.

Thalia’s partner network also provides the productization of chiplets in specific foundries, down to 7nm technology nodes.

If you are planning your own chiplet strategy, get in touch with us to find out how AMALIA platform can help to further simplify the IP reuse.

Artificial Intelligence is quite obviously a buzzword which attracts significant marketing hype – that has been the case for a decade at least. There are countless number of high-profile examples where AI is used to simply describe an automated (usually software-enabled) routine. Good examples of this can be seen in Facebook’s use of AI: filters that simply track and flag keywords, or images, that break a set of human-defined rules. The fact of the large number of false positives they ‘capture’ demonstrates that, while these programs may be artificial, they’re not always intelligent as we humans would define it. They are, more often than not, just forms of computational automation.

Don’t get me wrong, computational automation can be beneficial, it can speed things up and save significant time, hence money. But it does not add skills, nor does it bring added, intelligent value to a design team – which is what we’re trying to do for our customers. Given the wide and potentially misleading use of the term, there is no doubt that when we chose to use AI to refer to the capabilities of our AMALIA Design Enabler we really had to pause and check we were being honest with ourselves, and with our customers.

AMALIA Design Enabler passes the acid test. We threw problems at the system, asking it to find solutions to problems – looking for answers we didn’t know existed. In the video, you can see a perfect example of its application and the benefits of a truly-AI solution for supporting design problems: helping the designer to compare and assess alternative components to resolve a technical issue with the system. In this case, during a process migration, a very low current voltage regulator was taking far too long to achieve a zero temperature coefficient state… to compare the options and find a solution just in the small circuit in question could have taken the design team several weeks.

By entering the requirements into AMALIA Design Enabler, along with the options available, the Design Enabler AI algorithm was able to find its own way to the answer in relatively few steps and a very short amount of time: reaching the answer in just 40 steps, in spite of there being thousands of potential variables.

The reason we’re confident in calling the Design Enabler true-AI, is exactly that: the system is learning as it goes, changing direction based on initial findings and zeroing-in on the correct solution: it is not simply observing, calculating, and running every possible scenario before ‘happening’ upon the correct answer by brute force and computational power.

So, AI is dead. Long live AI! We believe that true-AI does have a place in design automation. Selecting the appropriate components and enabling appropriate IP reuse in process migration can be a complex, time-consuming task – but when it’s done well, it significantly improves design profitability and system performance.